Overview Block Diagram External Ports ![]() ![]() ![]() ![]() axi4lite_0 dlmb ilmb ![]() ![]() axi_v6_ddrx_0 dlmb_cntlr ilmb_cntlr ![]() axi_gpio_0 axi_gpio_1 axi_gpio_2 axi_gpio_3 axi_gpio_4 axi_iic_0 axi_sysace_0 axi_timer_0 axi_uart_0 mbref_mio_0 mbref_reg_0 ![]() clock_generator_0 proc_sys_reset_0 Timing Information |