Printable Version
Overview
Resources Used
1   MicroBlaze
2   Local Memory Bus (LMB) 1.0
2   AXI Interconnect
1   Block RAM (BRAM) Block
2   LMB BRAM Controller
1   AXI S6 Memory Controller(DDR/DDR2/DDR3)
1   AXI External Memory Controller (SRAM/Flash/Cellular RAM)
1   Processor System Reset Module
1   AXI Interrupt Controller
1   MicroBlaze Debug Module (MDM)
1   Clock Generator
1   AXI Timer/Counter
2   AXI UART (Lite)
4   AXI General Purpose IO
1   AXI 10/100 Ethernet MAC Lite
1   AXI IIC Interface
1   axi_mbref_reg
1   axi_mbref_mio
Specifics
Generated Mon Jan 20 19:49:46 2014
EDK Version 13.4
Device Family spartan6
Device xc6slx150tfgg676-3

Block Diagram TOP

BlockDiagram
External Ports TOP

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
SHARED fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET 
axi_emc_0 fpga_0_axi_emc_0_Mem_DQ_pin IO 15:0 fpga_0_axi_emc_0_Mem_DQ_pin
axi_emc_0 fpga_0_axi_emc_0_Mem_CEN_pin O 1 fpga_0_axi_emc_0_Mem_CEN_pin
axi_emc_0 fpga_0_axi_emc_0_Mem_OEN_pin O 1 fpga_0_axi_emc_0_Mem_OEN_pin
axi_emc_0 fpga_0_axi_emc_0_Mem_RPN_pin O 1 fpga_0_axi_emc_0_Mem_RPN_pin
axi_emc_0 fpga_0_axi_emc_0_Mem_WEN_pin O 1 fpga_0_axi_emc_0_Mem_WEN_pin
axi_ether_0 fpga_0_axi_ether_0_PHY_col I 1 fpga_0_axi_ether_0_PHY_col
axi_ether_0 fpga_0_axi_ether_0_PHY_crs I 1 fpga_0_axi_ether_0_PHY_crs
axi_ether_0 fpga_0_axi_ether_0_PHY_dv I 1 fpga_0_axi_ether_0_PHY_dv
axi_ether_0 fpga_0_axi_ether_0_PHY_rx_clk I 1 fpga_0_axi_ether_0_PHY_rx_clk
axi_ether_0 fpga_0_axi_ether_0_PHY_rx_data I 0:3 fpga_0_axi_ether_0_PHY_rx_data
axi_ether_0 fpga_0_axi_ether_0_PHY_rx_er I 1 fpga_0_axi_ether_0_PHY_rx_er
axi_ether_0 fpga_0_axi_ether_0_PHY_tx_clk I 1 fpga_0_axi_ether_0_PHY_tx_clk
axi_ether_0 fpga_0_axi_ether_0_PHY_MDIO IO 1 fpga_0_axi_ether_0_PHY_MDIO
axi_ether_0 fpga_0_axi_ether_0_PHY_MDC O 1 fpga_0_axi_ether_0_PHY_MDC
axi_ether_0 fpga_0_axi_ether_0_PHY_rst_n O 1 fpga_0_axi_ether_0_PHY_rst_n
axi_ether_0 fpga_0_axi_ether_0_PHY_tx_data O 0:3 fpga_0_axi_ether_0_PHY_tx_data
axi_ether_0 fpga_0_axi_ether_0_PHY_tx_en O 1 fpga_0_axi_ether_0_PHY_tx_en
axi_gpio_1 fpga_0_axi_gpio_1_GPIO_IO_pin I 0:2 fpga_0_axi_gpio_1_GPIO_IO_pin
axi_gpio_2 fpga_0_axi_gpio_2_GPIO_IO_pin I 0:7 fpga_0_axi_gpio_2_GPIO_IO_pin
axi_gpio_3 fpga_0_axi_gpio_3_GPIO_IO_pin O 0:7 fpga_0_axi_gpio_3_GPIO_IO_pin
axi_iic_0 fpga_0_axi_iic_0_Scl_pin IO 1 fpga_0_axi_iic_0_Scl_pin
axi_iic_0 fpga_0_axi_iic_0_Sda_pin IO 1 fpga_0_axi_iic_0_Sda_pin
axi_intc_0 fpga_0_RTC_Int_pin I 1 fpga_0_RTC_Int_pin  INTR 
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_dq_pin IO 0:15 fpga_0_axi_s6_ddrx_0_mcbx_dram_dq_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_n_pin IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_n_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_pin IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_n_pin IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_n_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_pin IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_rzq_pin IO 1 fpga_0_axi_s6_ddrx_0_rzq_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_zio_pin IO 1 fpga_0_axi_s6_ddrx_0_zio_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_addr_pin O 0:12 fpga_0_axi_s6_ddrx_0_mcbx_dram_addr_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_ba_pin O 0:2 fpga_0_axi_s6_ddrx_0_mcbx_dram_ba_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_cas_n_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_cas_n_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_cke_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_cke_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_n_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_n_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_ddr3_rst_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_ddr3_rst_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_ldm_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_ldm_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_odt_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_odt_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_ras_n_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_ras_n_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_udm_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_udm_pin
axi_s6_ddrx_0 fpga_0_axi_s6_ddrx_0_mcbx_dram_we_n_pin O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_we_n_pin
axi_uart_0 fpga_0_axi_uart_0_RX_pin I 1 fpga_0_axi_uart_0_RX_pin
axi_uart_0 fpga_0_axi_uart_0_TX_pin O 1 fpga_0_axi_uart_0_TX_pin
axi_uart_1 fpga_0_axi_uart_1_RX_pin I 1 fpga_0_axi_uart_1_RX_pin
axi_uart_1 fpga_0_axi_uart_1_TX_pin O 1 fpga_0_axi_uart_1_TX_pin
clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 dcm_clk_s  CLK 
Unconnected fpga_0_axi_emc_0_Mem_A_pin O 23:0 fpga_0_axi_emc_0_Mem_A_pin_vslice_0_23_concat
Unconnected fpga_0_RTC_Rst_pin O 1 net_vcc


Processors TOP

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor

IP Specs
Core Version Documentation
microblaze 8.20.b IP


microblaze_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_RESET I 1 proc_sys_reset_0_MB_Reset
1 CLK I 1 clk_83_3333MHzPLL0
2 INTERRUPT I 1 microblaze_0_interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXI_DP MASTER AXI axi4lite_0 14 Peripherals.
M_AXI_IP MASTER AXI axi4lite_0 14 Peripherals.
M_AXI_DC MASTER AXI axi4_0 axi_s6_ddrx_0
M_AXI_IC MASTER AXI axi4_0 axi_s6_ddrx_0
DLMB MASTER LMB dlmb dlmb_cntlr
ILMB MASTER LMB ilmb ilmb_cntlr
DEBUG TARGET XIL_MBDEBUG3 microblaze_0_debug mdm_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SCO 0
C_FREQ 0
C_DATA_SIZE 32
C_DYNAMIC_BUS_SIZING 1
C_FAMILY virtex5
C_INSTANCE microblaze
C_AVOID_PRIMITIVES 0
C_FAULT_TOLERANT 0
C_ECC_USE_CE_EXCEPTION 0
C_LOCKSTEP_SLAVE 0
C_ENDIANNESS 0
C_AREA_OPTIMIZED 0
C_OPTIMIZATION 0
C_INTERCONNECT 2
C_STREAM_INTERCONNECT 0
C_DPLB_DWIDTH 32
C_DPLB_NATIVE_DWIDTH 32
C_DPLB_BURST_EN 0
C_DPLB_P2P 0
C_IPLB_DWIDTH 32
C_IPLB_NATIVE_DWIDTH 32
C_IPLB_BURST_EN 0
C_IPLB_P2P 0
C_M_AXI_DP_SUPPORTS_THREADS 0
C_M_AXI_DP_THREAD_ID_WIDTH 1
C_M_AXI_DP_SUPPORTS_READ 1
C_M_AXI_DP_SUPPORTS_WRITE 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST 0
C_M_AXI_DP_DATA_WIDTH 32
C_M_AXI_DP_ADDR_WIDTH 32
C_M_AXI_DP_PROTOCOL AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
C_M_AXI_IP_SUPPORTS_THREADS 0
C_M_AXI_IP_THREAD_ID_WIDTH 1
C_M_AXI_IP_SUPPORTS_READ 1
C_M_AXI_IP_SUPPORTS_WRITE 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST 0
C_M_AXI_IP_DATA_WIDTH 32
C_M_AXI_IP_ADDR_WIDTH 32
C_M_AXI_IP_PROTOCOL AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
C_D_AXI 0
C_D_PLB 0
C_D_LMB 1
C_I_AXI 0
C_I_PLB 0
C_I_LMB 1
C_USE_MSR_INSTR 1
C_USE_PCMP_INSTR 1
C_USE_BARREL 1
C_USE_DIV 0
C_USE_HW_MUL 1
C_USE_FPU 0
C_UNALIGNED_EXCEPTIONS 0
C_ILL_OPCODE_EXCEPTION 0
C_M_AXI_I_BUS_EXCEPTION 0
C_M_AXI_D_BUS_EXCEPTION 0
C_IPLB_BUS_EXCEPTION 0
C_DPLB_BUS_EXCEPTION 0
C_DIV_ZERO_EXCEPTION 0
C_FPU_EXCEPTION 0
C_FSL_EXCEPTION 0
C_USE_STACK_PROTECTION 0
C_PVR 2
C_PVR_USER1 0x00
C_PVR_USER2 0x00000000
C_DEBUG_ENABLED 1
C_NUMBER_OF_PC_BRK 1
C_NUMBER_OF_RD_ADDR_BRK 0
C_NUMBER_OF_WR_ADDR_BRK 0
C_INTERRUPT_IS_EDGE 0
C_EDGE_IS_POSITIVE 1
C_RESET_MSR 0x00000000
C_OPCODE_0x0_ILLEGAL 0
C_FSL_LINKS 0
C_FSL_DATA_SIZE 32
C_USE_EXTENDED_FSL_INSTR 0
C_M0_AXIS_PROTOCOL GENERIC
C_S0_AXIS_PROTOCOL GENERIC
C_M1_AXIS_PROTOCOL GENERIC
C_S1_AXIS_PROTOCOL GENERIC
C_M2_AXIS_PROTOCOL GENERIC
C_S2_AXIS_PROTOCOL GENERIC
C_M3_AXIS_PROTOCOL GENERIC
C_S3_AXIS_PROTOCOL GENERIC
C_M4_AXIS_PROTOCOL GENERIC
C_S4_AXIS_PROTOCOL GENERIC
C_M5_AXIS_PROTOCOL GENERIC
C_S5_AXIS_PROTOCOL GENERIC
C_M6_AXIS_PROTOCOL GENERIC
C_S6_AXIS_PROTOCOL GENERIC
C_M7_AXIS_PROTOCOL GENERIC
C_S7_AXIS_PROTOCOL GENERIC
C_M8_AXIS_PROTOCOL GENERIC
C_S8_AXIS_PROTOCOL GENERIC
C_M9_AXIS_PROTOCOL GENERIC
C_S9_AXIS_PROTOCOL GENERIC
C_M10_AXIS_PROTOCOL GENERIC
C_S10_AXIS_PROTOCOL GENERIC
C_M11_AXIS_PROTOCOL GENERIC
C_S11_AXIS_PROTOCOL GENERIC
C_M12_AXIS_PROTOCOL GENERIC
C_S12_AXIS_PROTOCOL GENERIC
C_M13_AXIS_PROTOCOL GENERIC
C_S13_AXIS_PROTOCOL GENERIC
C_M14_AXIS_PROTOCOL GENERIC
 
Name Value
C_S14_AXIS_PROTOCOL GENERIC
C_M15_AXIS_PROTOCOL GENERIC
C_S15_AXIS_PROTOCOL GENERIC
C_M0_AXIS_DATA_WIDTH 32
C_S0_AXIS_DATA_WIDTH 32
C_M1_AXIS_DATA_WIDTH 32
C_S1_AXIS_DATA_WIDTH 32
C_M2_AXIS_DATA_WIDTH 32
C_S2_AXIS_DATA_WIDTH 32
C_M3_AXIS_DATA_WIDTH 32
C_S3_AXIS_DATA_WIDTH 32
C_M4_AXIS_DATA_WIDTH 32
C_S4_AXIS_DATA_WIDTH 32
C_M5_AXIS_DATA_WIDTH 32
C_S5_AXIS_DATA_WIDTH 32
C_M6_AXIS_DATA_WIDTH 32
C_S6_AXIS_DATA_WIDTH 32
C_M7_AXIS_DATA_WIDTH 32
C_S7_AXIS_DATA_WIDTH 32
C_M8_AXIS_DATA_WIDTH 32
C_S8_AXIS_DATA_WIDTH 32
C_M9_AXIS_DATA_WIDTH 32
C_S9_AXIS_DATA_WIDTH 32
C_M10_AXIS_DATA_WIDTH 32
C_S10_AXIS_DATA_WIDTH 32
C_M11_AXIS_DATA_WIDTH 32
C_S11_AXIS_DATA_WIDTH 32
C_M12_AXIS_DATA_WIDTH 32
C_S12_AXIS_DATA_WIDTH 32
C_M13_AXIS_DATA_WIDTH 32
C_S13_AXIS_DATA_WIDTH 32
C_M14_AXIS_DATA_WIDTH 32
C_S14_AXIS_DATA_WIDTH 32
C_M15_AXIS_DATA_WIDTH 32
C_S15_AXIS_DATA_WIDTH 32
C_ICACHE_BASEADDR 0x20000000
C_ICACHE_HIGHADDR 0x27FFFFFF
C_USE_ICACHE 1
C_ALLOW_ICACHE_WR 1
C_ADDR_TAG_BITS 17
C_CACHE_BYTE_SIZE 2048
C_ICACHE_USE_FSL 1
C_ICACHE_LINE_LEN 4
C_ICACHE_ALWAYS_USED 1
C_ICACHE_INTERFACE 0
C_ICACHE_VICTIMS 0
C_ICACHE_STREAMS 0
C_ICACHE_FORCE_TAG_LUTRAM 0
C_ICACHE_DATA_WIDTH 0
C_M_AXI_IC_SUPPORTS_THREADS 0
C_M_AXI_IC_THREAD_ID_WIDTH 1
C_M_AXI_IC_SUPPORTS_READ 1
C_M_AXI_IC_SUPPORTS_WRITE 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST 0
C_M_AXI_IC_DATA_WIDTH 32
C_M_AXI_IC_ADDR_WIDTH 32
C_M_AXI_IC_PROTOCOL AXI4
C_M_AXI_IC_USER_VALUE 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_IC_AWUSER_WIDTH 5
C_M_AXI_IC_ARUSER_WIDTH 5
C_M_AXI_IC_WUSER_WIDTH 1
C_M_AXI_IC_RUSER_WIDTH 1
C_M_AXI_IC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
C_DCACHE_BASEADDR 0x20000000
C_DCACHE_HIGHADDR 0x27FFFFFF
C_USE_DCACHE 1
C_ALLOW_DCACHE_WR 1
C_DCACHE_ADDR_TAG 17
C_DCACHE_BYTE_SIZE 2048
C_DCACHE_USE_FSL 1
C_DCACHE_LINE_LEN 4
C_DCACHE_ALWAYS_USED 1
C_DCACHE_INTERFACE 0
C_DCACHE_USE_WRITEBACK 0
C_DCACHE_VICTIMS 0
C_DCACHE_FORCE_TAG_LUTRAM 0
C_DCACHE_DATA_WIDTH 0
C_M_AXI_DC_SUPPORTS_THREADS 0
C_M_AXI_DC_THREAD_ID_WIDTH 1
C_M_AXI_DC_SUPPORTS_READ 1
C_M_AXI_DC_SUPPORTS_WRITE 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST 0
C_M_AXI_DC_DATA_WIDTH 32
C_M_AXI_DC_ADDR_WIDTH 32
C_M_AXI_DC_PROTOCOL AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS 0
C_M_AXI_DC_USER_VALUE 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_DC_AWUSER_WIDTH 5
C_M_AXI_DC_ARUSER_WIDTH 5
C_M_AXI_DC_WUSER_WIDTH 1
C_M_AXI_DC_RUSER_WIDTH 1
C_M_AXI_DC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
C_USE_MMU 3
C_MMU_DTLB_SIZE 4
C_MMU_ITLB_SIZE 2
C_MMU_TLB_ACCESS 3
C_MMU_ZONES 2
C_MMU_PRIVILEGED_INSTR 0
C_USE_INTERRUPT 0
C_USE_EXT_BRK 0
C_USE_EXT_NM_BRK 0
C_USE_BRANCH_TARGET_CACHE 0
C_BRANCH_TARGET_CACHE_SIZE 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Debuggers TOP

mdm_0   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

IP Specs
Core Version Documentation
mdm 2.00.b IP


mdm_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Debug_SYS_Rst O 1 proc_sys_reset_0_MB_Debug_Sys_Rst
1 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MBDEBUG_0 INITIATOR XIL_MBDEBUG3 microblaze_0_debug microblaze_0
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_JTAG_CHAIN 2
C_INTERCONNECT 2
C_BASEADDR 0x8FFF0000
C_HIGHADDR 0x8FFFFFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 3
 
Name Value
C_SPLB_NUM_MASTERS 8
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_MB_DBG_PORTS 1
C_USE_UART 1
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Interrupt Controllers TOP

axi_intc_0   AXI Interrupt Controller
intc core attached to the AXI

IP Specs
Core Version Documentation
axi_intc 1.01.a IP


axi_intc_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 IRQ O 1 microblaze_0_interrupt
1 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
2 INTR I 1 axi_iic_0_IIC2INTC_Irpt & axi_uart_1_Interrupt & axi_uart_0_Interrupt & axi_ether_0_IP2INTC_Irpt & fpga_0_RTC_Int_pin & axi_timer_0_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.
Interrupt Priorities
Priority SIG MODULE
0 axi_iic_0_IIC2INTC_Irpt axi_iic_0
1 axi_uart_1_Interrupt axi_uart_1
2 axi_uart_0_Interrupt axi_uart_0
3 axi_ether_0_IP2INTC_Irpt axi_ether_0
4 fpga_0_RTC_Int_pin EXTERNALPORTS
5 axi_timer_0_Interrupt axi_timer_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x8AFF0000
C_HIGHADDR 0x8AFFFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_NUM_INTR_INPUTS 2
C_KIND_OF_INTR 0xFFFFFFFF
C_KIND_OF_EDGE 0xFFFFFFFF
 
Name Value
C_KIND_OF_LVL 0xFFFFFFFF
C_HAS_IPR 1
C_HAS_SIE 1
C_HAS_CIE 1
C_HAS_IVR 1
C_IRQ_IS_LEVEL 1
C_IRQ_ACTIVE 1
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOP

axi4_0   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.05.a IP


axi4_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 interconnect_aclk I 1 clk_83_3333MHzPLL0
1 INTERCONNECT_ARESETN I 1 proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER M_AXI_DC
microblaze_0 MASTER M_AXI_IC
axi_s6_ddrx_0 SLAVE S0_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 1
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi4lite_0   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.05.a IP


axi4lite_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ARESETN I 1 proc_sys_reset_0_Interconnect_aresetn
1 INTERCONNECT_ACLK I 1 clk_83_3333MHzPLL0
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER M_AXI_DP
microblaze_0 MASTER M_AXI_IP
axi_intc_0 SLAVE S_AXI
mdm_0 SLAVE S_AXI
axi_timer_0 SLAVE S_AXI
axi_uart_0 SLAVE S_AXI
axi_uart_1 SLAVE S_AXI
axi_gpio_1 SLAVE S_AXI
axi_emc_0 SLAVE S_AXI_MEM
axi_gpio_3 SLAVE S_AXI
axi_ether_0 SLAVE S_AXI
axi_gpio_2 SLAVE S_AXI
axi_gpio_0 SLAVE S_AXI
axi_iic_0 SLAVE S_AXI
mbref_reg_0 SLAVE S_AXI
mbref_mio_0 SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 2.00.b IP


dlmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 SYS_RST I 1 proc_sys_reset_0_BUS_STRUCT_RESET
1 LMB_CLK I 1 clk_83_3333MHzPLL0
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DLMB
dlmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 2.00.b IP


ilmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 SYS_RST I 1 proc_sys_reset_0_BUS_STRUCT_RESET
1 LMB_CLK I 1 clk_83_3333MHzPLL0
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER ILMB
ilmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memorys TOP

lmb_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


lmb_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block ilmb_cntlr
PORTB TARGET XIL_BRAM microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block dlmb_cntlr


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memory Controllers TOP

axi_emc_0   AXI External Memory Controller (SRAM/Flash/Cellular RAM)
AXI External Memory Controller (SRAM/Flash/Cellular RAM)

IP Specs
Core Version Documentation
axi_emc 1.03.a IP


axi_emc_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 RdClk I 1 clk_83_3333MHzPLL0
2 Mem_WEN O 1 fpga_0_axi_emc_0_Mem_WEN_pin
3 Mem_RPN O 1 fpga_0_axi_emc_0_Mem_RPN_pin
4 Mem_OEN O 1 fpga_0_axi_emc_0_Mem_OEN_pin
5 Mem_DQ IO 1 fpga_0_axi_emc_0_Mem_DQ_pin
6 Mem_CEN O 1 fpga_0_axi_emc_0_Mem_CEN_pin
7 Mem_A O 1 0b0000000 & fpga_0_axi_emc_0_Mem_A_pin_vslice_0_23_concat & 0b0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI_MEM SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_EN_REG 0
C_S_AXI_REG_ADDR_WIDTH 32
C_S_AXI_REG_DATA_WIDTH 32
C_S_AXI_MEM_ID_WIDTH 4
C_S_AXI_MEM_ADDR_WIDTH 32
C_S_AXI_MEM_DATA_WIDTH 32
C_S_AXI_MEM_PROTOCOL axi4
C_S_AXI_REG_PROTOCOL axi4
C_AXI_CLK_PERIOD_PS 10000
C_LFLASH_PERIOD_PS 20000
C_LINEAR_FLASH_SYNC_BURST 0
C_NUM_BANKS_MEM 1
C_INCLUDE_NEGEDGE_IOREGS 0
C_MEM0_WIDTH 16
C_MEM1_WIDTH 32
C_MEM2_WIDTH 32
C_MEM3_WIDTH 32
C_INCLUDE_DATAWIDTH_MATCHING_0 1
C_INCLUDE_DATAWIDTH_MATCHING_1 0
C_INCLUDE_DATAWIDTH_MATCHING_2 0
C_INCLUDE_DATAWIDTH_MATCHING_3 0
C_MEM0_TYPE 2
C_SYNCH_PIPEDELAY_0 2
C_PARITY_TYPE_MEM_0 0
C_TCEDV_PS_MEM_0 130000
C_TAVDV_PS_MEM_0 130000
C_TPACC_PS_FLASH_0 25000
C_THZCE_PS_MEM_0 35000
C_THZOE_PS_MEM_0 7000
C_TWC_PS_MEM_0 13000
C_TWP_PS_MEM_0 70000
C_TWPH_PS_MEM_0 12000
C_TLZWE_PS_MEM_0 35000
C_WR_REC_TIME_MEM_0 100000
C_MEM1_TYPE 0
C_SYNCH_PIPEDELAY_1 2
C_PARITY_TYPE_MEM_1 0
C_TCEDV_PS_MEM_1 15000
C_TAVDV_PS_MEM_1 15000
C_TPACC_PS_FLASH_1 25000
C_THZCE_PS_MEM_1 7000
C_THZOE_PS_MEM_1 7000
 
Name Value
C_TWC_PS_MEM_1 15000
C_TWP_PS_MEM_1 12000
C_TWPH_PS_MEM_1 12000
C_TLZWE_PS_MEM_1 0
C_WR_REC_TIME_MEM_1 100000
C_MEM2_TYPE 0
C_SYNCH_PIPEDELAY_2 2
C_PARITY_TYPE_MEM_2 0
C_TCEDV_PS_MEM_2 15000
C_TAVDV_PS_MEM_2 15000
C_TPACC_PS_FLASH_2 25000
C_THZCE_PS_MEM_2 7000
C_THZOE_PS_MEM_2 7000
C_TWC_PS_MEM_2 15000
C_TWP_PS_MEM_2 12000
C_TWPH_PS_MEM_2 12000
C_TLZWE_PS_MEM_2 0
C_WR_REC_TIME_MEM_2 100000
C_MEM3_TYPE 0
C_SYNCH_PIPEDELAY_3 2
C_PARITY_TYPE_MEM_3 0
C_TCEDV_PS_MEM_3 15000
C_TAVDV_PS_MEM_3 15000
C_TPACC_PS_FLASH_3 25000
C_THZCE_PS_MEM_3 7000
C_THZOE_PS_MEM_3 7000
C_TWC_PS_MEM_3 15000
C_TWP_PS_MEM_3 12000
C_TWPH_PS_MEM_3 12000
C_TLZWE_PS_MEM_3 0
C_WR_REC_TIME_MEM_3 100000
C_MAX_MEM_WIDTH 16
C_S_AXI_REG_BASEADDR 0xFFFFFFFF
C_S_AXI_REG_HIGHADDR 0x00000000
C_S_AXI_MEM0_BASEADDR 0xAE000000
C_S_AXI_MEM0_HIGHADDR 0xAFFFFFFF
C_S_AXI_MEM1_BASEADDR 0xFFFFFFFF
C_S_AXI_MEM1_HIGHADDR 0x00000000
C_S_AXI_MEM2_BASEADDR 0xFFFFFFFF
C_S_AXI_MEM2_HIGHADDR 0x00000000
C_S_AXI_MEM3_BASEADDR 0xFFFFFFFF
C_S_AXI_MEM3_HIGHADDR 0x00000000
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_s6_ddrx_0   AXI S6 Memory Controller(DDR/DDR2/DDR3)
Spartan-6 memory controller

IP Specs
Core Version Documentation
axi_s6_ddrx 1.05.a IP


axi_s6_ddrx_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 zio IO 1 fpga_0_axi_s6_ddrx_0_zio_pin
1 rzq IO 1 fpga_0_axi_s6_ddrx_0_rzq_pin
2 s0_axi_aclk I 1 clk_83_3333MHzPLL0
3 ui_clk I 1 clk_83_3333MHzPLL0
4 mcbx_dram_we_n O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_we_n_pin
5 mcbx_dram_udqs_n IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_n_pin
6 mcbx_dram_udqs IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_pin
7 mcbx_dram_udm O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_udm_pin
8 mcbx_dram_ras_n O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_ras_n_pin
9 mcbx_dram_odt O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_odt_pin
10 mcbx_dram_ldm O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_ldm_pin
11 mcbx_dram_dqs_n IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_n_pin
12 mcbx_dram_dqs IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_pin
13 mcbx_dram_dq IO 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_dq_pin
14 mcbx_dram_ddr3_rst O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_ddr3_rst_pin
15 mcbx_dram_clk_n O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_n_pin
16 mcbx_dram_clk O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_pin
17 mcbx_dram_cke O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_cke_pin
18 mcbx_dram_cas_n O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_cas_n_pin
19 mcbx_dram_ba O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_ba_pin
20 mcbx_dram_addr O 1 fpga_0_axi_s6_ddrx_0_mcbx_dram_addr_pin
21 sysclk_2x I 1 clk_666_6667MHzPLL0_nobuf
22 sysclk_2x_180 I 1 clk_666_6667MHz180PLL0_nobuf
23 SYS_RST I 1 proc_sys_reset_0_BUS_STRUCT_RESET
24 PLL_LOCK I 1 proc_sys_reset_0_Dcm_locked
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S0_AXI SLAVE AXI axi4_0 microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MCB_LOC MEMC3
C_MCB_RZQ_LOC M4
C_MCB_ZIO_LOC H6
C_MCB_PERFORMANCE STANDARD
C_BYPASS_CORE_UCF 0
C_S0_AXI_BASEADDR 0x20000000
C_S0_AXI_HIGHADDR 0x27FFFFFF
C_S1_AXI_BASEADDR 0xFFFFFFFF
C_S1_AXI_HIGHADDR 0x00000000
C_S2_AXI_BASEADDR 0xFFFFFFFF
C_S2_AXI_HIGHADDR 0x00000000
C_S3_AXI_BASEADDR 0xFFFFFFFF
C_S3_AXI_HIGHADDR 0x00000000
C_S4_AXI_BASEADDR 0xFFFFFFFF
C_S4_AXI_HIGHADDR 0x00000000
C_S5_AXI_BASEADDR 0xFFFFFFFF
C_S5_AXI_HIGHADDR 0x00000000
C_MEM_TYPE DDR3
C_MEM_PARTNO MT41J64M16XX-187E
C_MEM_BASEPARTNO NOT_SET
C_NUM_DQ_PINS 16
C_MEM_ADDR_WIDTH 13
C_MEM_BANKADDR_WIDTH 3
C_MEM_NUM_COL_BITS 10
C_MEM_TRAS -1
C_MEM_TRCD -1
C_MEM_TREFI -1
C_MEM_TRFC -1
C_MEM_TRP -1
C_MEM_TWR -1
C_MEM_TRTP -1
C_MEM_TWTR -1
C_PORT_CONFIG B32_B32_B32_B32
C_SKIP_IN_TERM_CAL 0
C_SKIP_IN_TERM_CAL_VALUE NONE
C_MEMCLK_PERIOD 0
C_MEM_ADDR_ORDER ROW_BANK_COLUMN
C_MEM_TZQINIT_MAXCNT 512
C_MEM_CAS_LATENCY 6
C_SIMULATION TRUE
C_MEM_DDR1_2_ODS FULL
C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS CLASS_II
C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS CLASS_II
C_MEM_DDR2_RTT 150OHMS
C_MEM_DDR2_DIFF_DQS_EN YES
C_MEM_DDR2_3_PA_SR FULL
C_MEM_DDR2_3_HIGH_TEMP_SR NORMAL
C_MEM_DDR3_CAS_WR_LATENCY 5
C_MEM_DDR3_CAS_LATENCY 6
C_MEM_DDR3_ODS DIV6
C_MEM_DDR3_RTT DIV4
C_MEM_DDR3_AUTO_SR ENABLED
C_MEM_MOBILE_PA_SR FULL
C_MEM_MDDR_ODS FULL
C_ARB_ALGORITHM 0
C_ARB_NUM_TIME_SLOTS 12
C_ARB_TIME_SLOT_0 0b000000000001010011
C_ARB_TIME_SLOT_1 0b000000001010011000
C_ARB_TIME_SLOT_2 0b000000010011000001
C_ARB_TIME_SLOT_3 0b000000011000001010
C_ARB_TIME_SLOT_4 0b000000000001010011
C_ARB_TIME_SLOT_5 0b000000001010011000
C_ARB_TIME_SLOT_6 0b000000010011000001
C_ARB_TIME_SLOT_7 0b000000011000001010
C_ARB_TIME_SLOT_8 0b000000000001010011
C_ARB_TIME_SLOT_9 0b000000001010011000
C_ARB_TIME_SLOT_10 0b000000010011000001
C_ARB_TIME_SLOT_11 0b000000011000001010
C_S0_AXI_ENABLE 1
C_S0_AXI_PROTOCOL AXI4
C_S0_AXI_ID_WIDTH 4
C_S0_AXI_ADDR_WIDTH 32
C_S0_AXI_DATA_WIDTH 32
C_S0_AXI_SUPPORTS_READ 1
C_S0_AXI_SUPPORTS_WRITE 1
C_S0_AXI_SUPPORTS_NARROW_BURST 1
C_S0_AXI_REG_EN0 0x00000
C_S0_AXI_REG_EN1 0x01000
C_S0_AXI_STRICT_COHERENCY 1
C_S0_AXI_ENABLE_AP 0
 
Name Value
C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE 4
C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE 4
C_S1_AXI_ENABLE 0
C_S1_AXI_PROTOCOL AXI4
C_S1_AXI_ID_WIDTH 4
C_S1_AXI_ADDR_WIDTH 32
C_S1_AXI_DATA_WIDTH 32
C_S1_AXI_SUPPORTS_READ 1
C_S1_AXI_SUPPORTS_WRITE 1
C_S1_AXI_SUPPORTS_NARROW_BURST 1
C_S1_AXI_REG_EN0 0x00000
C_S1_AXI_REG_EN1 0x01000
C_S1_AXI_STRICT_COHERENCY 1
C_S1_AXI_ENABLE_AP 0
C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE 4
C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE 4
C_S2_AXI_ENABLE 0
C_S2_AXI_PROTOCOL AXI4
C_S2_AXI_ID_WIDTH 4
C_S2_AXI_ADDR_WIDTH 32
C_S2_AXI_DATA_WIDTH 32
C_S2_AXI_SUPPORTS_READ 1
C_S2_AXI_SUPPORTS_WRITE 1
C_S2_AXI_SUPPORTS_NARROW_BURST 1
C_S2_AXI_REG_EN0 0x00000
C_S2_AXI_REG_EN1 0x01000
C_S2_AXI_STRICT_COHERENCY 1
C_S2_AXI_ENABLE_AP 0
C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE 4
C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE 4
C_S3_AXI_ENABLE 0
C_S3_AXI_PROTOCOL AXI4
C_S3_AXI_ID_WIDTH 4
C_S3_AXI_ADDR_WIDTH 32
C_S3_AXI_DATA_WIDTH 32
C_S3_AXI_SUPPORTS_READ 1
C_S3_AXI_SUPPORTS_WRITE 1
C_S3_AXI_SUPPORTS_NARROW_BURST 1
C_S3_AXI_REG_EN0 0x00000
C_S3_AXI_REG_EN1 0x01000
C_S3_AXI_STRICT_COHERENCY 1
C_S3_AXI_ENABLE_AP 0
C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE 4
C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE 4
C_S4_AXI_ENABLE 0
C_S4_AXI_PROTOCOL AXI4
C_S4_AXI_ID_WIDTH 4
C_S4_AXI_ADDR_WIDTH 32
C_S4_AXI_DATA_WIDTH 32
C_S4_AXI_SUPPORTS_READ 1
C_S4_AXI_SUPPORTS_WRITE 1
C_S4_AXI_SUPPORTS_NARROW_BURST 1
C_S4_AXI_REG_EN0 0x00000
C_S4_AXI_REG_EN1 0x01000
C_S4_AXI_STRICT_COHERENCY 1
C_S4_AXI_ENABLE_AP 0
C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE 4
C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE 4
C_S5_AXI_ENABLE 0
C_S5_AXI_PROTOCOL AXI4
C_S5_AXI_ID_WIDTH 4
C_S5_AXI_ADDR_WIDTH 32
C_S5_AXI_DATA_WIDTH 32
C_S5_AXI_SUPPORTS_READ 1
C_S5_AXI_SUPPORTS_WRITE 1
C_S5_AXI_SUPPORTS_NARROW_BURST 1
C_S5_AXI_REG_EN0 0x00000
C_S5_AXI_REG_EN1 0x01000
C_S5_AXI_STRICT_COHERENCY 1
C_S5_AXI_ENABLE_AP 0
C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE 4
C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE 4
C_MCB_USE_EXTERNAL_BUFPLL 0
C_SYS_RST_PRESENT 0
C_INTERCONNECT_S0_AXI_MASTERS microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC
C_INTERCONNECT_S0_AXI_AW_REGISTER 8
C_INTERCONNECT_S0_AXI_AR_REGISTER 8
C_INTERCONNECT_S0_AXI_W_REGISTER 8
C_INTERCONNECT_S0_AXI_R_REGISTER 8
C_INTERCONNECT_S0_AXI_B_REGISTER 8
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


dlmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 3.00.b IP


dlmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block lmb_bram
SLMB SLAVE LMB dlmb microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00001FFF
C_FAMILY virtex5
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_ECC 0
C_INTERCONNECT 0
C_FAULT_INJECT 0
C_CE_FAILING_REGISTERS 0
C_UE_FAILING_REGISTERS 0
C_ECC_STATUS_REGISTERS 0
C_ECC_ONOFF_REGISTER 0
C_ECC_ONOFF_RESET_VALUE 1
C_CE_COUNTER_WIDTH 0
C_WRITE_ACCESS 2
 
Name Value
C_SPLB_CTRL_BASEADDR 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR 0x00000000
C_SPLB_CTRL_AWIDTH 32
C_SPLB_CTRL_DWIDTH 32
C_SPLB_CTRL_P2P 0
C_SPLB_CTRL_MID_WIDTH 1
C_SPLB_CTRL_NUM_MASTERS 1
C_SPLB_CTRL_SUPPORT_BURSTS 0
C_SPLB_CTRL_NATIVE_DWIDTH 32
C_SPLB_CTRL_CLK_FREQ_HZ 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ 100000000
C_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_S_AXI_CTRL_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ilmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 3.00.b IP


ilmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block lmb_bram
SLMB SLAVE LMB ilmb microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00001FFF
C_FAMILY virtex5
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_ECC 0
C_INTERCONNECT 0
C_FAULT_INJECT 0
C_CE_FAILING_REGISTERS 0
C_UE_FAILING_REGISTERS 0
C_ECC_STATUS_REGISTERS 0
C_ECC_ONOFF_REGISTER 0
C_ECC_ONOFF_RESET_VALUE 1
C_CE_COUNTER_WIDTH 0
C_WRITE_ACCESS 2
 
Name Value
C_SPLB_CTRL_BASEADDR 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR 0x00000000
C_SPLB_CTRL_AWIDTH 32
C_SPLB_CTRL_DWIDTH 32
C_SPLB_CTRL_P2P 0
C_SPLB_CTRL_MID_WIDTH 1
C_SPLB_CTRL_NUM_MASTERS 1
C_SPLB_CTRL_SUPPORT_BURSTS 0
C_SPLB_CTRL_NATIVE_DWIDTH 32
C_SPLB_CTRL_CLK_FREQ_HZ 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ 100000000
C_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_S_AXI_CTRL_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOP

axi_ether_0   AXI 10/100 Ethernet MAC Lite
'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'

IP Specs
Core Version Documentation
axi_ethernetlite 1.01.b IP


axi_ether_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 PHY_tx_en O 1 fpga_0_axi_ether_0_PHY_tx_en
2 PHY_tx_clk I 1 fpga_0_axi_ether_0_PHY_tx_clk
3 PHY_tx_data O 1 fpga_0_axi_ether_0_PHY_tx_data
4 PHY_rx_er I 1 fpga_0_axi_ether_0_PHY_rx_er
5 PHY_dv I 1 fpga_0_axi_ether_0_PHY_dv
6 PHY_rx_clk I 1 fpga_0_axi_ether_0_PHY_rx_clk
7 PHY_rx_data I 1 fpga_0_axi_ether_0_PHY_rx_data
8 PHY_rst_n O 1 fpga_0_axi_ether_0_PHY_rst_n
9 PHY_MDIO IO 1 fpga_0_axi_ether_0_PHY_MDIO
10 PHY_MDC O 1 fpga_0_axi_ether_0_PHY_MDC
11 PHY_crs I 1 fpga_0_axi_ether_0_PHY_crs
12 PHY_col I 1 fpga_0_axi_ether_0_PHY_col
13 IP2INTC_Irpt O 1 axi_ether_0_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_PROTOCOL AXI4
C_FAMILY virtex6
C_BASEADDR 0x88F00000
C_HIGHADDR 0x88F0FFFF
C_S_AXI_ACLK_PERIOD_PS 10000
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ID_WIDTH 4
C_INCLUDE_MDIO 1
 
Name Value
C_INCLUDE_GLOBAL_BUFFERS 0
C_INCLUDE_INTERNAL_LOOPBACK 0
C_DUPLEX 1
C_TX_PING_PONG 0
C_RX_PING_PONG 0
C_INCLUDE_PHY_CONSTRAINTS 1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE 1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE 1
C_S_AXI_SUPPORTS_NARROW_BURST 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_0   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 GPIO_IO_O O 1 internal_reset_request
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x80FF0000
C_HIGHADDR 0x80FFFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 1
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_1   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 GPIO_IO_I I 1 fpga_0_axi_gpio_1_GPIO_IO_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x80FE0000
C_HIGHADDR 0x80FEFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 3
C_GPIO2_WIDTH 32
C_ALL_INPUTS 1
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_2   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 GPIO_IO_I I 1 fpga_0_axi_gpio_2_GPIO_IO_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x80FD0000
C_HIGHADDR 0x80FDFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 1
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_gpio_3   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


axi_gpio_3 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 GPIO_IO_O O 1 fpga_0_axi_gpio_3_GPIO_IO_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x80FC0000
C_HIGHADDR 0x80FCFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_iic_0   AXI IIC Interface
AXI interface to Philips I2C bus v2.1

IP Specs
Core Version Documentation
axi_iic 1.01.b IP


axi_iic_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 Sda IO 1 fpga_0_axi_iic_0_Sda_pin
2 Scl IO 1 fpga_0_axi_iic_0_Scl_pin
3 IIC2INTC_Irpt O 1 axi_iic_0_IIC2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_BASEADDR 0x80EF0000
C_HIGHADDR 0x80EFFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_IIC_FREQ 100000
C_TEN_BIT_ADR 0
 
Name Value
C_GPO_WIDTH 1
C_S_AXI_ACLK_FREQ_HZ 25000000
C_SCL_INERTIAL_DELAY 0
C_SDA_INERTIAL_DELAY 0
C_SDA_LEVEL 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_timer_0   AXI Timer/Counter
Timer counter with AXI interface

IP Specs
Core Version Documentation
axi_timer 1.03.a IP


axi_timer_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 Interrupt O 1 axi_timer_0_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_PROTOCOL AXI4LITE
C_FAMILY virtex6
C_COUNT_WIDTH 32
C_ONE_TIMER_ONLY 0
C_TRIG0_ASSERT 1
C_TRIG1_ASSERT 1
 
Name Value
C_GEN0_ASSERT 1
C_GEN1_ASSERT 1
C_BASEADDR 0x8AEF0000
C_HIGHADDR 0x8AEFFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uart_0   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uart_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 TX O 1 fpga_0_axi_uart_0_TX_pin
2 RX I 1 fpga_0_axi_uart_0_RX_pin
3 Interrupt O 1 axi_uart_0_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x89FF0000
C_HIGHADDR 0x89FFFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_BAUDRATE 115200
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_uart_1   AXI UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.

IP Specs
Core Version Documentation
axi_uartlite 1.02.a IP


axi_uart_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
1 TX O 1 fpga_0_axi_uart_1_TX_pin
2 RX I 1 fpga_0_axi_uart_1_RX_pin
3 Interrupt O 1 axi_uart_1_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_S_AXI_ACLK_FREQ_HZ 100000000
C_BASEADDR 0x89FE0000
C_HIGHADDR 0x89FEFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
 
Name Value
C_BAUDRATE 115200
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 1
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


mbref_mio_0   axi_mbref_mio
MicroBlaze References simple memory bank for AXI4.

IP Specs
Core Version
axi_mbref_mio 1.00.a


mbref_mio_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_ID_WIDTH 4
C_RDATA_FIFO_DEPTH 0
C_INCLUDE_TIMEOUT_CNT 1
C_TIMEOUT_CNTR_VAL 8
C_ALIGN_BE_RDADDR 0
C_S_AXI_SUPPORTS_WRITE 1
C_S_AXI_SUPPORTS_READ 1
C_FAMILY virtex6
 
Name Value
C_S_AXI_MEM0_BASEADDR 0x80410000
C_S_AXI_MEM0_HIGHADDR 0x80410FFF
C_S_AXI_MEM1_BASEADDR 0x80411000
C_S_AXI_MEM1_HIGHADDR 0x80411FFF
C_S_AXI_MEM2_BASEADDR 0x80412000
C_S_AXI_MEM2_HIGHADDR 0x80412FFF
C_S_AXI_MEM3_BASEADDR 0x80413000
C_S_AXI_MEM3_HIGHADDR 0x80413FFF
C_S_AXI_PROTOCOL AXI4
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


mbref_reg_0   axi_mbref_reg
MicroBlaze References simple register bank for AXI4 Lite.

IP Specs
Core Version
axi_mbref_reg 1.00.a


mbref_reg_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_83_3333MHzPLL0
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_0 14 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_MIN_SIZE 0x000001FF
C_USE_WSTRB 0
C_DPHASE_TIMEOUT 8
C_BASEADDR 0x80800000
C_HIGHADDR 0x8080FFFF
 
Name Value
C_FAMILY virtex6
C_NUM_REG 1
C_NUM_MEM 1
C_SLV_AWIDTH 32
C_SLV_DWIDTH 32
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOP

clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 4.03.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LOCKED O 1 proc_sys_reset_0_Dcm_locked
1 CLKOUT2 O 1 clk_83_3333MHzPLL0
2 RST I 1 sys_rst_s
3 CLKOUT0 O 1 clk_666_6667MHzPLL0_nobuf
4 CLKOUT1 O 1 clk_666_6667MHz180PLL0_nobuf
5 CLKIN I 1 dcm_clk_s


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_DEVICE NOT_SET
C_PACKAGE NOT_SET
C_SPEEDGRADE NOT_SET
C_CLKIN_FREQ 100000000
C_CLKOUT0_FREQ 666666666
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP PLL0
C_CLKOUT0_BUF FALSE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 666666666
C_CLKOUT1_PHASE 180
C_CLKOUT1_GROUP PLL0
C_CLKOUT1_BUF FALSE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 83333333
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP PLL0
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 0
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 0
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP NONE
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 0
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
 
Name Value
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
C_PSDONE_GROUP NONE
C_EXT_RESET_HIGH 1
C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE
C_CLKOUT0_DUTY_CYCLE 0.500000
C_CLKOUT1_DUTY_CYCLE 0.500000
C_CLKOUT2_DUTY_CYCLE 0.500000
C_CLKOUT3_DUTY_CYCLE 0.500000
C_CLKOUT4_DUTY_CYCLE 0.500000
C_CLKOUT5_DUTY_CYCLE 0.500000
C_CLKOUT6_DUTY_CYCLE 0.500000
C_CLKOUT7_DUTY_CYCLE 0.500000
C_CLKOUT8_DUTY_CYCLE 0.500000
C_CLKOUT9_DUTY_CYCLE 0.500000
C_CLKOUT10_DUTY_CYCLE 0.500000
C_CLKOUT11_DUTY_CYCLE 0.500000
C_CLKOUT12_DUTY_CYCLE 0.500000
C_CLKOUT13_DUTY_CYCLE 0.500000
C_CLKOUT14_DUTY_CYCLE 0.500000
C_CLKOUT15_DUTY_CYCLE 0.500000
C_CLK_GEN UPDATE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 3.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_Debug_Sys_Rst I 1 proc_sys_reset_0_MB_Debug_Sys_Rst
1 Dcm_locked I 1 proc_sys_reset_0_Dcm_locked
2 MB_Reset O 1 proc_sys_reset_0_MB_Reset
3 Slowest_sync_clk I 1 clk_83_3333MHzPLL0
4 Interconnect_aresetn O 1 proc_sys_reset_0_Interconnect_aresetn
5 Ext_Reset_In I 1 sys_rst_s
6 BUS_STRUCT_RESET O 1 proc_sys_reset_0_BUS_STRUCT_RESET
7 Aux_Reset_In I 1 internal_reset_request


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY lx
C_EXT_RST_WIDTH 4
C_AUX_RST_WIDTH 4
C_EXT_RESET_HIGH 1
C_AUX_RESET_HIGH 1
C_NUM_BUS_RST 1
C_NUM_PERP_RST 1
C_NUM_INTERCONNECT_ARESETN 1
C_NUM_PERP_ARESETN 1
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOP


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.