# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
SHARED
|
fpga_0_rst_1_sys_rst_pin |
I |
1 |
sys_rst_s |
RESET |
axi_emc_0
|
fpga_0_axi_emc_0_Mem_DQ_pin |
IO |
15:0 |
fpga_0_axi_emc_0_Mem_DQ_pin |
|
axi_emc_0
|
fpga_0_axi_emc_0_Mem_CEN_pin |
O |
1 |
fpga_0_axi_emc_0_Mem_CEN_pin |
|
axi_emc_0
|
fpga_0_axi_emc_0_Mem_OEN_pin |
O |
1 |
fpga_0_axi_emc_0_Mem_OEN_pin |
|
axi_emc_0
|
fpga_0_axi_emc_0_Mem_RPN_pin |
O |
1 |
fpga_0_axi_emc_0_Mem_RPN_pin |
|
axi_emc_0
|
fpga_0_axi_emc_0_Mem_WEN_pin |
O |
1 |
fpga_0_axi_emc_0_Mem_WEN_pin |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_col |
I |
1 |
fpga_0_axi_ether_0_PHY_col |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_crs |
I |
1 |
fpga_0_axi_ether_0_PHY_crs |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_dv |
I |
1 |
fpga_0_axi_ether_0_PHY_dv |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_rx_clk |
I |
1 |
fpga_0_axi_ether_0_PHY_rx_clk |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_rx_data |
I |
0:3 |
fpga_0_axi_ether_0_PHY_rx_data |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_rx_er |
I |
1 |
fpga_0_axi_ether_0_PHY_rx_er |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_tx_clk |
I |
1 |
fpga_0_axi_ether_0_PHY_tx_clk |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_MDIO |
IO |
1 |
fpga_0_axi_ether_0_PHY_MDIO |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_MDC |
O |
1 |
fpga_0_axi_ether_0_PHY_MDC |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_rst_n |
O |
1 |
fpga_0_axi_ether_0_PHY_rst_n |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_tx_data |
O |
0:3 |
fpga_0_axi_ether_0_PHY_tx_data |
|
axi_ether_0
|
fpga_0_axi_ether_0_PHY_tx_en |
O |
1 |
fpga_0_axi_ether_0_PHY_tx_en |
|
axi_gpio_1
|
fpga_0_axi_gpio_1_GPIO_IO_pin |
I |
0:2 |
fpga_0_axi_gpio_1_GPIO_IO_pin |
|
axi_gpio_2
|
fpga_0_axi_gpio_2_GPIO_IO_pin |
I |
0:7 |
fpga_0_axi_gpio_2_GPIO_IO_pin |
|
axi_gpio_3
|
fpga_0_axi_gpio_3_GPIO_IO_pin |
O |
0:7 |
fpga_0_axi_gpio_3_GPIO_IO_pin |
|
axi_iic_0
|
fpga_0_axi_iic_0_Scl_pin |
IO |
1 |
fpga_0_axi_iic_0_Scl_pin |
|
axi_iic_0
|
fpga_0_axi_iic_0_Sda_pin |
IO |
1 |
fpga_0_axi_iic_0_Sda_pin |
|
axi_intc_0
|
fpga_0_RTC_Int_pin |
I |
1 |
fpga_0_RTC_Int_pin |
INTR |
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_dq_pin |
IO |
0:15 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_dq_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_n_pin |
IO |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_n_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_pin |
IO |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_dqs_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_n_pin |
IO |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_n_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_pin |
IO |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_udqs_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_rzq_pin |
IO |
1 |
fpga_0_axi_s6_ddrx_0_rzq_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_zio_pin |
IO |
1 |
fpga_0_axi_s6_ddrx_0_zio_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_addr_pin |
O |
0:12 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_addr_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_ba_pin |
O |
0:2 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_ba_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_cas_n_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_cas_n_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_cke_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_cke_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_n_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_n_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_clk_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_ddr3_rst_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_ddr3_rst_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_ldm_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_ldm_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_odt_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_odt_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_ras_n_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_ras_n_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_udm_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_udm_pin |
|
axi_s6_ddrx_0
|
fpga_0_axi_s6_ddrx_0_mcbx_dram_we_n_pin |
O |
1 |
fpga_0_axi_s6_ddrx_0_mcbx_dram_we_n_pin |
|
axi_uart_0
|
fpga_0_axi_uart_0_RX_pin |
I |
1 |
fpga_0_axi_uart_0_RX_pin |
|
axi_uart_0
|
fpga_0_axi_uart_0_TX_pin |
O |
1 |
fpga_0_axi_uart_0_TX_pin |
|
axi_uart_1
|
fpga_0_axi_uart_1_RX_pin |
I |
1 |
fpga_0_axi_uart_1_RX_pin |
|
axi_uart_1
|
fpga_0_axi_uart_1_TX_pin |
O |
1 |
fpga_0_axi_uart_1_TX_pin |
|
clock_generator_0
|
fpga_0_clk_1_sys_clk_pin |
I |
1 |
dcm_clk_s |
CLK |
Unconnected
|
fpga_0_axi_emc_0_Mem_A_pin |
O |
23:0 |
fpga_0_axi_emc_0_Mem_A_pin_vslice_0_23_concat |
|
Unconnected
|
fpga_0_RTC_Rst_pin |
O |
1 |
net_vcc |
|