TABLE OF CONTENTS
Overview Block Diagram External Ports Processor microblaze_0 Debuggers mdm_0 Interrupt Controllers axi_intc_0 Busses axi4_0 axi4lite_0 dlmb ilmb Memory lmb_bram Memory Controllers axi_emc_0 axi_v6_ddrx_0 dlmb_cntlr ilmb_cntlr Peripherals axi_ether_0 axi_gpio_0 axi_gpio_1 axi_gpio_2 axi_gpio_3 axi_gpio_4 axi_iic_0 axi_sysace_0 axi_timer_0 axi_uart_0 mbref_mio_0 mbref_reg_0 IP axi_emc_0_CE_inverter clock_generator_0 proc_sys_reset_0 Timing Information

Overview | TOC Resources Used
1 | MicroBlaze
2 | Local Memory Bus (LMB) 1.0
2 | AXI Interconnect
1 | Block RAM (BRAM) Block
2 | LMB BRAM Controller
1 | AXI V6 Memory Controller(DDR2/DDR3)
1 | AXI External Memory Controller (SRAM/Flash/Cellular RAM)
1 | Processor System Reset Module
1 | MicroBlaze Debug Module (MDM)
1 | axi_mbref_reg
1 | Clock Generator
1 | AXI UART (Lite)
1 | AXI Timer/Counter
1 | AXI System ACE Interface Controller(Compact Flash)
1 | AXI Interrupt Controller
1 | AXI IIC Interface
5 | AXI General Purpose IO
1 | AXI 10/100 Ethernet MAC Lite
1 | Utility Vector Logic
1 | axi_mbref_mio
| Specifics
Generated | Tue Jan 21 02:53:47 2014
EDK Version | 13.4
Device Family | virtex6
Device | xc6vlx240tff1156-1
Block Diagram | TOC
External Ports | TOC
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
SHARED | fpga_0_axi_sysace_0_SysACE_MPIRQ_pin | I | 1 | fpga_0_axi_sysace_0_SysACE_MPIRQ_pin | INTR
SHARED | fpga_0_rst_1_sys_rst_pin | I | 1 | sys_rst_s | RESET
axi_emc_0 | fpga_0_axi_emc_0_Mem_DQ_pin | IO | 15:0 | fpga_0_axi_emc_0_Mem_DQ_pin |
axi_emc_0 | fpga_0_axi_emc_0_Mem_OEN_pin | O | 1 | fpga_0_axi_emc_0_Mem_OEN_pin |
axi_emc_0 | fpga_0_axi_emc_0_Mem_WEN_pin | O | 1 | fpga_0_axi_emc_0_Mem_WEN_pin |
axi_emc_0_CE_inverter | fpga_0_axi_emc_0_CE_inverter_Res_pin | O | 1 | fpga_0_axi_emc_0_CE_inverter_Res_pin |
axi_ether_0 | fpga_0_axi_ether_0_PHY_col | I | 1 | fpga_0_axi_ether_0_PHY_col |
axi_ether_0 | fpga_0_axi_ether_0_PHY_crs | I | 1 | fpga_0_axi_ether_0_PHY_crs |
axi_ether_0 | fpga_0_axi_ether_0_PHY_dv | I | 1 | fpga_0_axi_ether_0_PHY_dv |
axi_ether_0 | fpga_0_axi_ether_0_PHY_rx_clk | I | 1 | fpga_0_axi_ether_0_PHY_rx_clk |
axi_ether_0 | fpga_0_axi_ether_0_PHY_rx_data | I | 0:3 | fpga_0_axi_ether_0_PHY_rx_data |
axi_ether_0 | fpga_0_axi_ether_0_PHY_rx_er | I | 1 | fpga_0_axi_ether_0_PHY_rx_er |
axi_ether_0 | fpga_0_axi_ether_0_PHY_tx_clk | I | 1 | fpga_0_axi_ether_0_PHY_tx_clk |
axi_ether_0 | fpga_0_axi_ether_0_PHY_MDIO | IO | 1 | fpga_0_axi_ether_0_PHY_MDIO |
axi_ether_0 | fpga_0_axi_ether_0_PHY_MDC | O | 1 | fpga_0_axi_ether_0_PHY_MDC |
axi_ether_0 | fpga_0_axi_ether_0_PHY_rst_n | O | 1 | fpga_0_axi_ether_0_PHY_rst_n |
axi_ether_0 | fpga_0_axi_ether_0_PHY_tx_data | O | 0:3 | fpga_0_axi_ether_0_PHY_tx_data |
axi_ether_0 | fpga_0_axi_ether_0_PHY_tx_en | O | 1 | fpga_0_axi_ether_0_PHY_tx_en |
axi_gpio_1 | fpga_0_axi_gpio_1_GPIO_IO_pin | I | 4:0 | fpga_0_axi_gpio_1_GPIO_IO_pin |
axi_gpio_2 | fpga_0_axi_gpio_2_GPIO_IO_pin | I | 7:0 | fpga_0_axi_gpio_2_GPIO_IO_pin |
axi_gpio_3 | fpga_0_axi_gpio_3_GPIO_IO_pin | O | 7:0 | fpga_0_axi_gpio_3_GPIO_IO_pin |
axi_gpio_4 | fpga_0_axi_gpio_4_GPIO_IO_pin | O | 4:0 | fpga_0_axi_gpio_4_GPIO_IO_pin |
axi_iic_0 | fpga_0_axi_iic_0_Scl_pin | IO | 1 | fpga_0_axi_iic_0_Scl_pin |
axi_iic_0 | fpga_0_axi_iic_0_Sda_pin | IO | 1 | fpga_0_axi_iic_0_Sda_pin |
axi_sysace_0 | fpga_0_axi_sysace_0_SysACE_CLK_pin | I | 1 | fpga_0_axi_sysace_0_SysACE_CLK_pin |
axi_sysace_0 | fpga_0_axi_sysace_0_SysACE_MPD_pin | IO | 0:15 | fpga_0_axi_sysace_0_SysACE_MPD_pin |
axi_sysace_0 | fpga_0_axi_sysace_0_SysACE_CEN_pin | O | 1 | fpga_0_axi_sysace_0_SysACE_CEN_pin |
axi_sysace_0 | fpga_0_axi_sysace_0_SysACE_MPA_pin | O | 0:6 | fpga_0_axi_sysace_0_SysACE_MPA_pin |
axi_sysace_0 | fpga_0_axi_sysace_0_SysACE_OEN_pin | O | 1 | fpga_0_axi_sysace_0_SysACE_OEN_pin |
axi_sysace_0 | fpga_0_axi_sysace_0_SysACE_WEN_pin | O | 1 | fpga_0_axi_sysace_0_SysACE_WEN_pin |
axi_uart_0 | fpga_0_axi_uart_0_RX_pin | I | 1 | fpga_0_axi_uart_0_RX_pin |
axi_uart_0 | fpga_0_axi_uart_0_TX_pin | O | 1 | fpga_0_axi_uart_0_TX_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_dq_pin | IO | 0:63 | fpga_0_axi_v6_ddrx_0_ddr_dq_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_dqs_n_pin | IO | 0:7 | fpga_0_axi_v6_ddrx_0_ddr_dqs_n_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_dqs_p_pin | IO | 0:7 | fpga_0_axi_v6_ddrx_0_ddr_dqs_p_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_addr_pin | O | 0:12 | fpga_0_axi_v6_ddrx_0_ddr_addr_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_ba_pin | O | 0:2 | fpga_0_axi_v6_ddrx_0_ddr_ba_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_cas_n_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_cas_n_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_cke_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_cke_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_clk_n_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_clk_n_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_clk_p_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_clk_p_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_cs_n_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_cs_n_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_dm_pin | O | 0:7 | fpga_0_axi_v6_ddrx_0_ddr_dm_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_odt_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_odt_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_ras_n_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_ras_n_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_reset_n_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_reset_n_pin |
axi_v6_ddrx_0 | fpga_0_axi_v6_ddrx_0_ddr_we_n_pin | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_we_n_pin |
clock_generator_0 | fpga_0_clk_1_sys_clk_n_pin | I | 1 | dcm_clk_s | CLK
clock_generator_0 | fpga_0_clk_1_sys_clk_p_pin | I | 1 | dcm_clk_s | CLK
Unconnected | fpga_0_axi_emc_0_Mem_A_pin | O | 23:0 | fpga_0_axi_emc_0_Mem_A_pin_vslice_0_23_concat |
Processors | TOC
microblaze_0 MicroBlaze The MicroBlaze 32 bit soft processor
IP Specs
Core | Version | Documentation
microblaze | 8.20.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MB_RESET | I | 1 | proc_sys_reset_0_MB_Reset
1 | CLK | I | 1 | clk_100_0000MHzMMCM0
2 | INTERRUPT | I | 1 | microblaze_0_interrupt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
M_AXI_DP | MASTER | AXI | axi4lite_0 | 15 Peripherals.
M_AXI_IP | MASTER | AXI | axi4lite_0 | 15 Peripherals.
M_AXI_DC | MASTER | AXI | axi4_0 | axi_v6_ddrx_0
M_AXI_IC | MASTER | AXI | axi4_0 | axi_v6_ddrx_0
DLMB | MASTER | LMB | dlmb | dlmb_cntlr
ILMB | MASTER | LMB | ilmb | ilmb_cntlr
DEBUG | TARGET | XIL_MBDEBUG3 | microblaze_0_debug | mdm_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SCO | 0
C_FREQ | 0
C_DATA_SIZE | 32
C_DYNAMIC_BUS_SIZING | 1
C_FAMILY | virtex5
C_INSTANCE | microblaze
C_AVOID_PRIMITIVES | 0
C_FAULT_TOLERANT | 0
C_ECC_USE_CE_EXCEPTION | 0
C_LOCKSTEP_SLAVE | 0
C_ENDIANNESS | 0
C_AREA_OPTIMIZED | 0
C_OPTIMIZATION | 0
C_INTERCONNECT | 2
C_STREAM_INTERCONNECT | 0
C_DPLB_DWIDTH | 32
C_DPLB_NATIVE_DWIDTH | 32
C_DPLB_BURST_EN | 0
C_DPLB_P2P | 0
C_IPLB_DWIDTH | 32
C_IPLB_NATIVE_DWIDTH | 32
C_IPLB_BURST_EN | 0
C_IPLB_P2P | 0
C_M_AXI_DP_SUPPORTS_THREADS | 0
C_M_AXI_DP_THREAD_ID_WIDTH | 1
C_M_AXI_DP_SUPPORTS_READ | 1
C_M_AXI_DP_SUPPORTS_WRITE | 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DP_DATA_WIDTH | 32
C_M_AXI_DP_ADDR_WIDTH | 32
C_M_AXI_DP_PROTOCOL | AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS | 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING | 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING | 1
C_M_AXI_IP_SUPPORTS_THREADS | 0
C_M_AXI_IP_THREAD_ID_WIDTH | 1
C_M_AXI_IP_SUPPORTS_READ | 1
C_M_AXI_IP_SUPPORTS_WRITE | 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IP_DATA_WIDTH | 32
C_M_AXI_IP_ADDR_WIDTH | 32
C_M_AXI_IP_PROTOCOL | AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING | 1
C_D_AXI | 0
C_D_PLB | 0
C_D_LMB | 1
C_I_AXI | 0
C_I_PLB | 0
C_I_LMB | 1
C_USE_MSR_INSTR | 1
C_USE_PCMP_INSTR | 1
C_USE_BARREL | 1
C_USE_DIV | 0
C_USE_HW_MUL | 1
C_USE_FPU | 0
C_UNALIGNED_EXCEPTIONS | 0
C_ILL_OPCODE_EXCEPTION | 0
C_M_AXI_I_BUS_EXCEPTION | 0
C_M_AXI_D_BUS_EXCEPTION | 0
C_IPLB_BUS_EXCEPTION | 0
C_DPLB_BUS_EXCEPTION | 0
C_DIV_ZERO_EXCEPTION | 0
C_FPU_EXCEPTION | 0
C_FSL_EXCEPTION | 0
C_USE_STACK_PROTECTION | 0
C_PVR | 2
C_PVR_USER1 | 0x00
C_PVR_USER2 | 0x00000000
C_DEBUG_ENABLED | 1
C_NUMBER_OF_PC_BRK | 1
C_NUMBER_OF_RD_ADDR_BRK | 0
C_NUMBER_OF_WR_ADDR_BRK | 0
C_INTERRUPT_IS_EDGE | 0
C_EDGE_IS_POSITIVE | 1
C_RESET_MSR | 0x00000000
C_OPCODE_0x0_ILLEGAL | 0
C_FSL_LINKS | 0
C_FSL_DATA_SIZE | 32
C_USE_EXTENDED_FSL_INSTR | 0
C_M0_AXIS_PROTOCOL | GENERIC
C_S0_AXIS_PROTOCOL | GENERIC
C_M1_AXIS_PROTOCOL | GENERIC
C_S1_AXIS_PROTOCOL | GENERIC
C_M2_AXIS_PROTOCOL | GENERIC
C_S2_AXIS_PROTOCOL | GENERIC
C_M3_AXIS_PROTOCOL | GENERIC
C_S3_AXIS_PROTOCOL | GENERIC
C_M4_AXIS_PROTOCOL | GENERIC
C_S4_AXIS_PROTOCOL | GENERIC
C_M5_AXIS_PROTOCOL | GENERIC
C_S5_AXIS_PROTOCOL | GENERIC
C_M6_AXIS_PROTOCOL | GENERIC
C_S6_AXIS_PROTOCOL | GENERIC
C_M7_AXIS_PROTOCOL | GENERIC
C_S7_AXIS_PROTOCOL | GENERIC
C_M8_AXIS_PROTOCOL | GENERIC
C_S8_AXIS_PROTOCOL | GENERIC
C_M9_AXIS_PROTOCOL | GENERIC
C_S9_AXIS_PROTOCOL | GENERIC
C_M10_AXIS_PROTOCOL | GENERIC
C_S10_AXIS_PROTOCOL | GENERIC
C_M11_AXIS_PROTOCOL | GENERIC
C_S11_AXIS_PROTOCOL | GENERIC
C_M12_AXIS_PROTOCOL | GENERIC
C_S12_AXIS_PROTOCOL | GENERIC
C_M13_AXIS_PROTOCOL | GENERIC
C_S13_AXIS_PROTOCOL | GENERIC
C_M14_AXIS_PROTOCOL | GENERIC
C_S14_AXIS_PROTOCOL | GENERIC |  | Name | Value
C_M15_AXIS_PROTOCOL | GENERIC
C_S15_AXIS_PROTOCOL | GENERIC
C_M0_AXIS_DATA_WIDTH | 32
C_S0_AXIS_DATA_WIDTH | 32
C_M1_AXIS_DATA_WIDTH | 32
C_S1_AXIS_DATA_WIDTH | 32
C_M2_AXIS_DATA_WIDTH | 32
C_S2_AXIS_DATA_WIDTH | 32
C_M3_AXIS_DATA_WIDTH | 32
C_S3_AXIS_DATA_WIDTH | 32
C_M4_AXIS_DATA_WIDTH | 32
C_S4_AXIS_DATA_WIDTH | 32
C_M5_AXIS_DATA_WIDTH | 32
C_S5_AXIS_DATA_WIDTH | 32
C_M6_AXIS_DATA_WIDTH | 32
C_S6_AXIS_DATA_WIDTH | 32
C_M7_AXIS_DATA_WIDTH | 32
C_S7_AXIS_DATA_WIDTH | 32
C_M8_AXIS_DATA_WIDTH | 32
C_S8_AXIS_DATA_WIDTH | 32
C_M9_AXIS_DATA_WIDTH | 32
C_S9_AXIS_DATA_WIDTH | 32
C_M10_AXIS_DATA_WIDTH | 32
C_S10_AXIS_DATA_WIDTH | 32
C_M11_AXIS_DATA_WIDTH | 32
C_S11_AXIS_DATA_WIDTH | 32
C_M12_AXIS_DATA_WIDTH | 32
C_S12_AXIS_DATA_WIDTH | 32
C_M13_AXIS_DATA_WIDTH | 32
C_S13_AXIS_DATA_WIDTH | 32
C_M14_AXIS_DATA_WIDTH | 32
C_S14_AXIS_DATA_WIDTH | 32
C_M15_AXIS_DATA_WIDTH | 32
C_S15_AXIS_DATA_WIDTH | 32
C_ICACHE_BASEADDR | 0x20000000
C_ICACHE_HIGHADDR | 0x2FFFFFFF
C_USE_ICACHE | 1
C_ALLOW_ICACHE_WR | 1
C_ADDR_TAG_BITS | 17
C_CACHE_BYTE_SIZE | 2048
C_ICACHE_USE_FSL | 1
C_ICACHE_LINE_LEN | 4
C_ICACHE_ALWAYS_USED | 1
C_ICACHE_INTERFACE | 0
C_ICACHE_VICTIMS | 0
C_ICACHE_STREAMS | 0
C_ICACHE_FORCE_TAG_LUTRAM | 0
C_ICACHE_DATA_WIDTH | 0
C_M_AXI_IC_SUPPORTS_THREADS | 0
C_M_AXI_IC_THREAD_ID_WIDTH | 1
C_M_AXI_IC_SUPPORTS_READ | 1
C_M_AXI_IC_SUPPORTS_WRITE | 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IC_DATA_WIDTH | 32
C_M_AXI_IC_ADDR_WIDTH | 32
C_M_AXI_IC_PROTOCOL | AXI4
C_M_AXI_IC_USER_VALUE | 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_IC_AWUSER_WIDTH | 5
C_M_AXI_IC_ARUSER_WIDTH | 5
C_M_AXI_IC_WUSER_WIDTH | 1
C_M_AXI_IC_RUSER_WIDTH | 1
C_M_AXI_IC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING | 2
C_DCACHE_BASEADDR | 0x20000000
C_DCACHE_HIGHADDR | 0x2FFFFFFF
C_USE_DCACHE | 1
C_ALLOW_DCACHE_WR | 1
C_DCACHE_ADDR_TAG | 17
C_DCACHE_BYTE_SIZE | 2048
C_DCACHE_USE_FSL | 1
C_DCACHE_LINE_LEN | 4
C_DCACHE_ALWAYS_USED | 1
C_DCACHE_INTERFACE | 0
C_DCACHE_USE_WRITEBACK | 0
C_DCACHE_VICTIMS | 0
C_DCACHE_FORCE_TAG_LUTRAM | 0
C_DCACHE_DATA_WIDTH | 0
C_M_AXI_DC_SUPPORTS_THREADS | 0
C_M_AXI_DC_THREAD_ID_WIDTH | 1
C_M_AXI_DC_SUPPORTS_READ | 1
C_M_AXI_DC_SUPPORTS_WRITE | 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DC_DATA_WIDTH | 32
C_M_AXI_DC_ADDR_WIDTH | 32
C_M_AXI_DC_PROTOCOL | AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS | 0
C_M_AXI_DC_USER_VALUE | 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_DC_AWUSER_WIDTH | 5
C_M_AXI_DC_ARUSER_WIDTH | 5
C_M_AXI_DC_WUSER_WIDTH | 1
C_M_AXI_DC_RUSER_WIDTH | 1
C_M_AXI_DC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING | 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING | 32
C_USE_MMU | 3
C_MMU_DTLB_SIZE | 4
C_MMU_ITLB_SIZE | 2
C_MMU_TLB_ACCESS | 3
C_MMU_ZONES | 2
C_MMU_PRIVILEGED_INSTR | 0
C_USE_INTERRUPT | 0
C_USE_EXT_BRK | 0
C_USE_EXT_NM_BRK | 0
C_USE_BRANCH_TARGET_CACHE | 0
C_BRANCH_TARGET_CACHE_SIZE | 0
C_INTERCONNECT_M_AXI_DC_AW_REGISTER | 0
C_INTERCONNECT_M_AXI_DC_W_REGISTER | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Debuggers | TOC
mdm_0 MicroBlaze Debug Module (MDM) Debug module for MicroBlaze Soft Processor.
IP Specs
Core | Version | Documentation
mdm | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
1 | Debug_SYS_Rst | O | 1 | proc_sys_reset_0_MB_Debug_Sys_Rst
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
MBDEBUG_0 | INITIATOR | XIL_MBDEBUG3 | microblaze_0_debug | microblaze_0
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_JTAG_CHAIN | 2
C_INTERCONNECT | 2
C_BASEADDR | 0x8FFF0000
C_HIGHADDR | 0x8FFFFFFF
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_P2P | 0
C_SPLB_MID_WIDTH | 3 |  | Name | Value
C_SPLB_NUM_MASTERS | 8
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_SUPPORT_BURSTS | 0
C_MB_DBG_PORTS | 1
C_USE_UART | 1
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Interrupt Controllers | TOC
axi_intc_0 AXI Interrupt Controller intc core attached to the AXI
IP Specs
Core | Version | Documentation
axi_intc | 1.01.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | IRQ | O | 1 | microblaze_0_interrupt
1 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
2 | INTR | I | 1 | axi_iic_0_IIC2INTC_Irpt & axi_uart_0_Interrupt & axi_ether_0_IP2INTC_Irpt & fpga_0_axi_sysace_0_SysACE_MPIRQ_pin & axi_sysace_0_SysACE_IRQ & axi_timer_0_Interrupt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Interrupt Priorities
Priority | SIG | MODULE
0 | axi_iic_0_IIC2INTC_Irpt | axi_iic_0
1 | axi_uart_0_Interrupt | axi_uart_0
2 | axi_ether_0_IP2INTC_Irpt | axi_ether_0
3 | fpga_0_axi_sysace_0_SysACE_MPIRQ_pin | EXTERNALPORTS
4 | axi_sysace_0_SysACE_IRQ | axi_sysace_0
5 | axi_timer_0_Interrupt | axi_timer_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x8AFF0000
C_HIGHADDR | 0x8AFFFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_NUM_INTR_INPUTS | 2
C_KIND_OF_INTR | 0xFFFFFFFF
C_KIND_OF_EDGE | 0xFFFFFFFF |  | Name | Value
C_KIND_OF_LVL | 0xFFFFFFFF
C_HAS_IPR | 1
C_HAS_SIE | 1
C_HAS_CIE | 1
C_HAS_IVR | 1
C_IRQ_IS_LEVEL | 1
C_IRQ_ACTIVE | 1
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Busses | TOC
axi4_0 AXI Interconnect AXI4 Memory-Mapped Interconnect
IP Specs
Core | Version | Documentation
axi_interconnect | 1.05.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | interconnect_aclk | I | 1 | clk_100_0000MHzMMCM0
1 | INTERCONNECT_ARESETN | I | 1 | proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | M_AXI_DC
microblaze_0 | MASTER | M_AXI_IC
axi_v6_ddrx_0 | SLAVE | S_AXI
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | rtl
C_BASEFAMILY | rtl
C_NUM_SLAVE_SLOTS | 1
C_NUM_MASTER_SLOTS | 1
C_AXI_ID_WIDTH | 1
C_AXI_ADDR_WIDTH | 32
C_AXI_DATA_MAX_WIDTH | 32
C_S_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR |
C_M_AXI_HIGH_ADDR |
C_S_AXI_BASE_ID | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT | 0b0000000000000000
C_S_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_M_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO | 1
C_S_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_S_AXI_SUPPORTS_READ | 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_M_AXI_SUPPORTS_READ | 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS | 0
C_AXI_AWUSER_WIDTH | 1
C_AXI_ARUSER_WIDTH | 1
C_AXI_WUSER_WIDTH | 1
C_AXI_RUSER_WIDTH | 1
C_AXI_BUSER_WIDTH | 1
C_AXI_CONNECTIVITY | 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD | 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING | 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 |  | Name | Value
C_M_AXI_READ_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE | 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_S_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER | 0
C_INTERCONNECT_CONNECTIVITY_MODE | 1
C_USE_CTRL_PORT | 0
C_USE_INTERRUPT | 1
C_RANGE_CHECK | 2
C_S_AXI_CTRL_PROTOCOL | AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_BASEADDR | 0xFFFFFFFF
C_HIGHADDR | 0x00000000
C_DEBUG | 0
C_S_AXI_DEBUG_SLOT | 0
C_M_AXI_DEBUG_SLOT | 0
C_MAX_DEBUG_THREADS | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi4lite_0 AXI Interconnect AXI4 Memory-Mapped Interconnect
IP Specs
Core | Version | Documentation
axi_interconnect | 1.05.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | INTERCONNECT_ARESETN | I | 1 | proc_sys_reset_0_Interconnect_aresetn
1 | INTERCONNECT_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | M_AXI_DP
microblaze_0 | MASTER | M_AXI_IP
mdm_0 | SLAVE | S_AXI
mbref_reg_0 | SLAVE | S_AXI
axi_uart_0 | SLAVE | S_AXI
axi_timer_0 | SLAVE | S_AXI
axi_sysace_0 | SLAVE | S_AXI
axi_intc_0 | SLAVE | S_AXI
axi_iic_0 | SLAVE | S_AXI
axi_gpio_4 | SLAVE | S_AXI
axi_gpio_3 | SLAVE | S_AXI
axi_gpio_2 | SLAVE | S_AXI
axi_gpio_1 | SLAVE | S_AXI
axi_gpio_0 | SLAVE | S_AXI
axi_ether_0 | SLAVE | S_AXI
axi_emc_0 | SLAVE | S_AXI_MEM
mbref_mio_0 | SLAVE | S_AXI
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | rtl
C_BASEFAMILY | rtl
C_NUM_SLAVE_SLOTS | 1
C_NUM_MASTER_SLOTS | 1
C_AXI_ID_WIDTH | 1
C_AXI_ADDR_WIDTH | 32
C_AXI_DATA_MAX_WIDTH | 32
C_S_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR |
C_M_AXI_HIGH_ADDR |
C_S_AXI_BASE_ID | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT | 0b0000000000000000
C_S_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_M_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO | 1
C_S_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_S_AXI_SUPPORTS_READ | 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_M_AXI_SUPPORTS_READ | 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS | 0
C_AXI_AWUSER_WIDTH | 1
C_AXI_ARUSER_WIDTH | 1
C_AXI_WUSER_WIDTH | 1
C_AXI_RUSER_WIDTH | 1
C_AXI_BUSER_WIDTH | 1
C_AXI_CONNECTIVITY | 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD | 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING | 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 |  | Name | Value
C_M_AXI_READ_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE | 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_S_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER | 0
C_INTERCONNECT_CONNECTIVITY_MODE | 0
C_USE_CTRL_PORT | 0
C_USE_INTERRUPT | 1
C_RANGE_CHECK | 2
C_S_AXI_CTRL_PROTOCOL | AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_BASEADDR | 0xFFFFFFFF
C_HIGHADDR | 0x00000000
C_DEBUG | 0
C_S_AXI_DEBUG_SLOT | 0
C_M_AXI_DEBUG_SLOT | 0
C_MAX_DEBUG_THREADS | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
dlmb Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | SYS_RST | I | 1 | proc_sys_reset_0_BUS_STRUCT_RESET
1 | LMB_CLK | I | 1 | clk_100_0000MHzMMCM0
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | DLMB
dlmb_cntlr | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
ilmb Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | SYS_RST | I | 1 | proc_sys_reset_0_BUS_STRUCT_RESET
1 | LMB_CLK | I | 1 | clk_100_0000MHzMMCM0
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | ILMB
ilmb_cntlr | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Memorys | TOC
lmb_bram Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
IP Specs
Core | Version | Documentation
bram_block | 1.00.a | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | TARGET | XIL_BRAM | microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block | ilmb_cntlr
PORTB | TARGET | XIL_BRAM | microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block | dlmb_cntlr
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEMSIZE | 2048
C_PORT_DWIDTH | 32
C_PORT_AWIDTH | 32
C_NUM_WE | 4
C_FAMILY | virtex2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Memory Controllers | TOC
axi_emc_0 AXI External Memory Controller (SRAM/Flash/Cellular RAM) AXI External Memory Controller (SRAM/Flash/Cellular RAM)
IP Specs
Core | Version | Documentation
axi_emc | 1.03.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | Mem_CEN | O | 1 | fpga_0_axi_emc_0_Mem_CEN_invertor_Op1_Adhoc
1 | Mem_A | O | 1 | 0b0000000 & fpga_0_axi_emc_0_Mem_A_pin_vslice_0_23_concat & 0b0
2 | Mem_DQ | IO | 1 | fpga_0_axi_emc_0_Mem_DQ_pin
3 | Mem_OEN | O | 1 | fpga_0_axi_emc_0_Mem_OEN_pin
4 | Mem_WEN | O | 1 | fpga_0_axi_emc_0_Mem_WEN_pin
5 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
6 | RdClk | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI_MEM | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_S_AXI_EN_REG | 0
C_S_AXI_REG_ADDR_WIDTH | 32
C_S_AXI_REG_DATA_WIDTH | 32
C_S_AXI_MEM_ID_WIDTH | 4
C_S_AXI_MEM_ADDR_WIDTH | 32
C_S_AXI_MEM_DATA_WIDTH | 32
C_S_AXI_MEM_PROTOCOL | axi4
C_S_AXI_REG_PROTOCOL | axi4
C_AXI_CLK_PERIOD_PS | 10000
C_LFLASH_PERIOD_PS | 20000
C_LINEAR_FLASH_SYNC_BURST | 0
C_NUM_BANKS_MEM | 1
C_INCLUDE_NEGEDGE_IOREGS | 0
C_MEM0_WIDTH | 16
C_MEM1_WIDTH | 32
C_MEM2_WIDTH | 32
C_MEM3_WIDTH | 32
C_INCLUDE_DATAWIDTH_MATCHING_0 | 1
C_INCLUDE_DATAWIDTH_MATCHING_1 | 0
C_INCLUDE_DATAWIDTH_MATCHING_2 | 0
C_INCLUDE_DATAWIDTH_MATCHING_3 | 0
C_MEM0_TYPE | 2
C_SYNCH_PIPEDELAY_0 | 2
C_PARITY_TYPE_MEM_0 | 0
C_TCEDV_PS_MEM_0 | 130000
C_TAVDV_PS_MEM_0 | 130000
C_TPACC_PS_FLASH_0 | 25000
C_THZCE_PS_MEM_0 | 35000
C_THZOE_PS_MEM_0 | 7000
C_TWC_PS_MEM_0 | 13000
C_TWP_PS_MEM_0 | 70000
C_TWPH_PS_MEM_0 | 12000
C_TLZWE_PS_MEM_0 | 35000
C_WR_REC_TIME_MEM_0 | 100000
C_MEM1_TYPE | 0
C_SYNCH_PIPEDELAY_1 | 2
C_PARITY_TYPE_MEM_1 | 0
C_TCEDV_PS_MEM_1 | 15000
C_TAVDV_PS_MEM_1 | 15000
C_TPACC_PS_FLASH_1 | 25000
C_THZCE_PS_MEM_1 | 7000
C_THZOE_PS_MEM_1 | 7000 |  | Name | Value
C_TWC_PS_MEM_1 | 15000
C_TWP_PS_MEM_1 | 12000
C_TWPH_PS_MEM_1 | 12000
C_TLZWE_PS_MEM_1 | 0
C_WR_REC_TIME_MEM_1 | 100000
C_MEM2_TYPE | 0
C_SYNCH_PIPEDELAY_2 | 2
C_PARITY_TYPE_MEM_2 | 0
C_TCEDV_PS_MEM_2 | 15000
C_TAVDV_PS_MEM_2 | 15000
C_TPACC_PS_FLASH_2 | 25000
C_THZCE_PS_MEM_2 | 7000
C_THZOE_PS_MEM_2 | 7000
C_TWC_PS_MEM_2 | 15000
C_TWP_PS_MEM_2 | 12000
C_TWPH_PS_MEM_2 | 12000
C_TLZWE_PS_MEM_2 | 0
C_WR_REC_TIME_MEM_2 | 100000
C_MEM3_TYPE | 0
C_SYNCH_PIPEDELAY_3 | 2
C_PARITY_TYPE_MEM_3 | 0
C_TCEDV_PS_MEM_3 | 15000
C_TAVDV_PS_MEM_3 | 15000
C_TPACC_PS_FLASH_3 | 25000
C_THZCE_PS_MEM_3 | 7000
C_THZOE_PS_MEM_3 | 7000
C_TWC_PS_MEM_3 | 15000
C_TWP_PS_MEM_3 | 12000
C_TWPH_PS_MEM_3 | 12000
C_TLZWE_PS_MEM_3 | 0
C_WR_REC_TIME_MEM_3 | 100000
C_MAX_MEM_WIDTH | 16
C_S_AXI_REG_BASEADDR | 0xFFFFFFFF
C_S_AXI_REG_HIGHADDR | 0x00000000
C_S_AXI_MEM0_BASEADDR | 0xAE000000
C_S_AXI_MEM0_HIGHADDR | 0xAFFFFFFF
C_S_AXI_MEM1_BASEADDR | 0xFFFFFFFF
C_S_AXI_MEM1_HIGHADDR | 0x00000000
C_S_AXI_MEM2_BASEADDR | 0xFFFFFFFF
C_S_AXI_MEM2_HIGHADDR | 0x00000000
C_S_AXI_MEM3_BASEADDR | 0xFFFFFFFF
C_S_AXI_MEM3_HIGHADDR | 0x00000000
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_v6_ddrx_0 AXI V6 Memory Controller(DDR2/DDR3) Virtex-6 memory controller.
IP Specs
Core | Version | Documentation
axi_v6_ddrx | 1.05.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | ddr_ck_p | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_clk_p_pin
1 | ddr_ck_n | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_clk_n_pin
2 | ddr_cke | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_cke_pin
3 | ddr_cs_n | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_cs_n_pin
4 | ddr_odt | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_odt_pin
5 | ddr_ras_n | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_ras_n_pin
6 | ddr_cas_n | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_cas_n_pin
7 | ddr_we_n | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_we_n_pin
8 | ddr_dm | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_dm_pin
9 | ddr_ba | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_ba_pin
10 | ddr_addr | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_addr_pin
11 | ddr_reset_n | O | 1 | fpga_0_axi_v6_ddrx_0_ddr_reset_n_pin
12 | ddr_dq | IO | 1 | fpga_0_axi_v6_ddrx_0_ddr_dq_pin
13 | ddr_dqs_p | IO | 1 | fpga_0_axi_v6_ddrx_0_ddr_dqs_p_pin
14 | ddr_dqs_n | IO | 1 | fpga_0_axi_v6_ddrx_0_ddr_dqs_n_pin
15 | clk | I | 1 | clk_200_0000MHzMMCM0
16 | clk_ref | I | 1 | clk_200_0000MHzMMCM0
17 | clk_mem | I | 1 | clk_400_0000MHzMMCM0
18 | clk_rd_base | I | 1 | clk_400_0000MHzMMCM0_nobuf_varphase
19 | PD_PSEN | O | 1 | psen
20 | PD_PSINCDEC | O | 1 | psincdec
21 | PD_PSDONE | I | 1 | psdone
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4_0 | microblaze_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEM_PARTNO | MT4JSF6464HY-1G1
C_MEM_BASEPARTNO | NOT_SET
C_REFCLK_FREQ | 200
C_BYPASS_INIT_CAL | FAST
C_IODELAY_GRP | IODELAY_MIG
C_USE_EXTERNAL_IODELAY_CTRL | 0
C_DRAM_TYPE | DDR3
C_NCS_PER_RANK | 1
C_BANK_WIDTH | 3
C_CK_WIDTH | 1
C_CKE_WIDTH | 1
C_COL_WIDTH | 10
C_CS_WIDTH | 1
C_DM_WIDTH | 8
C_USE_DM_PORT | 1
C_DRAM_WIDTH | 8
C_DQS_WIDTH | 8
C_ROW_WIDTH | 13
C_DQ_WIDTH | 64
C_BURST_MODE | 8
C_BURST_TYPE | SEQ
C_IODELAY_HP_MODE | ON
C_CL | 6
C_CWL | 5
C_ADDR_CMD_MODE | 1T
C_NBANK_MACHS | 4
C_ORDERING | NORM
C_RANKS | 1
C_CAL_WIDTH | HALF
C_RTT_NOM | 40
C_RTT_WR | OFF
C_OUTPUT_DRV | HIGH
C_REG_CTRL | OFF
C_NDQS_COL0 | 3
C_NDQS_COL1 | 5
C_NDQS_COL2 | 0
C_NDQS_COL3 | 0
C_DQS_LOC_COL0 | 0x000000000000000000000000000000020100
C_DQS_LOC_COL1 | 0x000000000000000000000000000706050403
C_DQS_LOC_COL2 | 0x000000000000000000000000000000000000
C_DQS_LOC_COL3 | 0x000000000000000000000000000000000000
C_TCK | 0 |  | Name | Value
C_TFAW | -1
C_TPRDI | -1
C_TRRD | -1
C_TRAS | -1
C_TRCD | -1
C_TREFI | -1
C_TRFC | -1
C_TRP | -1
C_TRTP | -1
C_TWTR | -1
C_TZQI | -1
C_TZQCS | -1
C_SLOT_0_CONFIG | 0b00000001
C_SLOT_1_CONFIG | 0b00000000
C_MEM_ADDR_ORDER | BANK_ROW_COLUMN
C_ECC | OFF
C_ECC_TEST | OFF
C_S_AXI_ID_WIDTH | 4
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_SUPPORTS_NARROW_BURST | 1
C_S_AXI_REG_EN0 | 0x00000
C_S_AXI_REG_EN1 | 0x01000
C_RD_WR_ARB_ALGORITHM | RD_PRI_REG
C_S_AXI_BASEADDR | 0x20000000
C_S_AXI_HIGHADDR | 0x2FFFFFFF
C_S_AXI_PROTOCOL | AXI4
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE | 4
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE | 4
C_S_AXI_CTRL_PROTOCOL | AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_ECC_ONOFF_RESET_VALUE | 1
C_MMCM_EXT_LOC | MMCM_ADV_X0Y8
C_INTERCONNECT_S_AXI_AR_REGISTER | 1
C_INTERCONNECT_S_AXI_AW_REGISTER | 1
C_INTERCONNECT_S_AXI_R_REGISTER | 1
C_INTERCONNECT_S_AXI_W_REGISTER | 1
C_INTERCONNECT_S_AXI_B_REGISTER | 1
C_INTERCONNECT_S_AXI_MASTERS | microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
dlmb_cntlr LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.00.b | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
BRAM_PORT | INITIATOR | XIL_BRAM | microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block | lmb_bram
SLMB | SLAVE | LMB | dlmb | microblaze_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x00001FFF
C_FAMILY | virtex5
C_MASK | 0x00800000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0
C_WRITE_ACCESS | 2 |  | Name | Value
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
ilmb_cntlr LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.00.b | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
BRAM_PORT | INITIATOR | XIL_BRAM | microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block | lmb_bram
SLMB | SLAVE | LMB | ilmb | microblaze_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x00001FFF
C_FAMILY | virtex5
C_MASK | 0x00800000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0
C_WRITE_ACCESS | 2 |  | Name | Value
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Peripherals | TOC
axi_ether_0 AXI 10/100 Ethernet MAC Lite 'IEEE Std. 802.3 MII interface MAC with AXI interface, lightweight implementation'
IP Specs
Core | Version | Documentation
axi_ethernetlite | 1.01.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | PHY_MDIO | IO | 1 | fpga_0_axi_ether_0_PHY_MDIO
1 | PHY_MDC | O | 1 | fpga_0_axi_ether_0_PHY_MDC
2 | PHY_tx_data | O | 1 | fpga_0_axi_ether_0_PHY_tx_data
3 | PHY_tx_en | O | 1 | fpga_0_axi_ether_0_PHY_tx_en
4 | PHY_tx_clk | I | 1 | fpga_0_axi_ether_0_PHY_tx_clk
5 | PHY_col | I | 1 | fpga_0_axi_ether_0_PHY_col
6 | PHY_rx_data | I | 1 | fpga_0_axi_ether_0_PHY_rx_data
7 | PHY_rx_er | I | 1 | fpga_0_axi_ether_0_PHY_rx_er
8 | PHY_rx_clk | I | 1 | fpga_0_axi_ether_0_PHY_rx_clk
9 | PHY_crs | I | 1 | fpga_0_axi_ether_0_PHY_crs
10 | PHY_dv | I | 1 | fpga_0_axi_ether_0_PHY_dv
11 | PHY_rst_n | O | 1 | fpga_0_axi_ether_0_PHY_rst_n
12 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
13 | IP2INTC_Irpt | O | 1 | axi_ether_0_IP2INTC_Irpt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_PROTOCOL | AXI4
C_FAMILY | virtex6
C_BASEADDR | 0x88F00000
C_HIGHADDR | 0x88F0FFFF
C_S_AXI_ACLK_PERIOD_PS | 10000
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_ID_WIDTH | 4
C_INCLUDE_MDIO | 1 |  | Name | Value
C_INCLUDE_GLOBAL_BUFFERS | 0
C_INCLUDE_INTERNAL_LOOPBACK | 0
C_DUPLEX | 1
C_TX_PING_PONG | 0
C_RX_PING_PONG | 0
C_INCLUDE_PHY_CONSTRAINTS | 1
C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE | 1
C_INTERCONNECT_S_AXI_READ_ACCEPTANCE | 1
C_S_AXI_SUPPORTS_NARROW_BURST | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_gpio_0 AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus.
IP Specs
Core | Version | Documentation
axi_gpio | 1.01.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | GPIO_IO_O | O | 1 | internal_reset_request
1 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x80FF0000
C_HIGHADDR | 0x80FFFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_GPIO_WIDTH | 1
C_GPIO2_WIDTH | 32
C_ALL_INPUTS | 0 |  | Name | Value
C_ALL_INPUTS_2 | 0
C_INTERRUPT_PRESENT | 0
C_DOUT_DEFAULT | 0x00000000
C_TRI_DEFAULT | 0xFFFFFFFF
C_IS_DUAL | 0
C_DOUT_DEFAULT_2 | 0x00000000
C_TRI_DEFAULT_2 | 0xFFFFFFFF
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_gpio_1 AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus.
IP Specs
Core | Version | Documentation
axi_gpio | 1.01.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | GPIO_IO_I | I | 1 | fpga_0_axi_gpio_1_GPIO_IO_pin
1 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x80FE0000
C_HIGHADDR | 0x80FEFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_GPIO_WIDTH | 5
C_GPIO2_WIDTH | 32
C_ALL_INPUTS | 1 |  | Name | Value
C_ALL_INPUTS_2 | 0
C_INTERRUPT_PRESENT | 0
C_DOUT_DEFAULT | 0x00000000
C_TRI_DEFAULT | 0xFFFFFFFF
C_IS_DUAL | 0
C_DOUT_DEFAULT_2 | 0x00000000
C_TRI_DEFAULT_2 | 0xFFFFFFFF
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_gpio_2 AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus.
IP Specs
Core | Version | Documentation
axi_gpio | 1.01.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | GPIO_IO_I | I | 1 | fpga_0_axi_gpio_2_GPIO_IO_pin
1 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x80FD0000
C_HIGHADDR | 0x80FDFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_GPIO_WIDTH | 8
C_GPIO2_WIDTH | 32
C_ALL_INPUTS | 1 |  | Name | Value
C_ALL_INPUTS_2 | 0
C_INTERRUPT_PRESENT | 0
C_DOUT_DEFAULT | 0x00000000
C_TRI_DEFAULT | 0xFFFFFFFF
C_IS_DUAL | 0
C_DOUT_DEFAULT_2 | 0x00000000
C_TRI_DEFAULT_2 | 0xFFFFFFFF
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_gpio_3 AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus.
IP Specs
Core | Version | Documentation
axi_gpio | 1.01.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | GPIO_IO_O | O | 1 | fpga_0_axi_gpio_3_GPIO_IO_pin
1 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x80FC0000
C_HIGHADDR | 0x80FCFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_GPIO_WIDTH | 8
C_GPIO2_WIDTH | 32
C_ALL_INPUTS | 0 |  | Name | Value
C_ALL_INPUTS_2 | 0
C_INTERRUPT_PRESENT | 0
C_DOUT_DEFAULT | 0x00000000
C_TRI_DEFAULT | 0xFFFFFFFF
C_IS_DUAL | 0
C_DOUT_DEFAULT_2 | 0x00000000
C_TRI_DEFAULT_2 | 0xFFFFFFFF
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_gpio_4 AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus.
IP Specs
Core | Version | Documentation
axi_gpio | 1.01.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | GPIO_IO_O | O | 1 | fpga_0_axi_gpio_4_GPIO_IO_pin
1 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x80FB0000
C_HIGHADDR | 0x80FBFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_GPIO_WIDTH | 5
C_GPIO2_WIDTH | 32
C_ALL_INPUTS | 0 |  | Name | Value
C_ALL_INPUTS_2 | 0
C_INTERRUPT_PRESENT | 0
C_DOUT_DEFAULT | 0x00000000
C_TRI_DEFAULT | 0xFFFFFFFF
C_IS_DUAL | 0
C_DOUT_DEFAULT_2 | 0x00000000
C_TRI_DEFAULT_2 | 0xFFFFFFFF
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_iic_0 AXI IIC Interface AXI interface to Philips I2C bus v2.1
IP Specs
Core | Version | Documentation
axi_iic | 1.01.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
1 | Sda | IO | 1 | fpga_0_axi_iic_0_Sda_pin
2 | Scl | IO | 1 | fpga_0_axi_iic_0_Scl_pin
3 | IIC2INTC_Irpt | O | 1 | axi_iic_0_IIC2INTC_Irpt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x80EF0000
C_HIGHADDR | 0x80EFFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_IIC_FREQ | 100000
C_TEN_BIT_ADR | 0 |  | Name | Value
C_GPO_WIDTH | 1
C_S_AXI_ACLK_FREQ_HZ | 25000000
C_SCL_INERTIAL_DELAY | 0
C_SDA_INERTIAL_DELAY | 0
C_SDA_LEVEL | 1
C_S_AXI_PROTOCOL | AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_sysace_0 AXI System ACE Interface Controller(Compact Flash) Interface between the AXI and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral
IP Specs
Core | Version | Documentation
axi_sysace | 1.01.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
1 | SysACE_CLK | I | 1 | fpga_0_axi_sysace_0_SysACE_CLK_pin
2 | SysACE_MPIRQ | I | 1 | fpga_0_axi_sysace_0_SysACE_MPIRQ_pin
3 | SysACE_MPA | O | 1 | fpga_0_axi_sysace_0_SysACE_MPA_pin
4 | SysACE_CEN | O | 1 | fpga_0_axi_sysace_0_SysACE_CEN_pin
5 | SysACE_OEN | O | 1 | fpga_0_axi_sysace_0_SysACE_OEN_pin
6 | SysACE_WEN | O | 1 | fpga_0_axi_sysace_0_SysACE_WEN_pin
7 | SysACE_MPD | IO | 1 | fpga_0_axi_sysace_0_SysACE_MPD_pin
8 | SysACE_IRQ | O | 1 | axi_sysace_0_SysACE_IRQ
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_PROTOCOL | AXI4LITE
C_FAMILY | virtex6
C_BASEADDR | 0x83600000
C_HIGHADDR | 0x8360FFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_MEM_WIDTH | 16 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_timer_0 AXI Timer/Counter Timer counter with AXI interface
IP Specs
Core | Version | Documentation
axi_timer | 1.03.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
1 | Interrupt | O | 1 | axi_timer_0_Interrupt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_PROTOCOL | AXI4LITE
C_FAMILY | virtex6
C_COUNT_WIDTH | 32
C_ONE_TIMER_ONLY | 0
C_TRIG0_ASSERT | 1
C_TRIG1_ASSERT | 1 |  | Name | Value
C_GEN0_ASSERT | 1
C_GEN1_ASSERT | 1
C_BASEADDR | 0x8AEF0000
C_HIGHADDR | 0x8AEFFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_uart_0 AXI UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.
IP Specs
Core | Version | Documentation
axi_uartlite | 1.02.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | TX | O | 1 | fpga_0_axi_uart_0_TX_pin
1 | RX | I | 1 | fpga_0_axi_uart_0_RX_pin
2 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
3 | Interrupt | O | 1 | axi_uart_0_Interrupt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_S_AXI_ACLK_FREQ_HZ | 100000000
C_BASEADDR | 0x89FF0000
C_HIGHADDR | 0x89FFFFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32 |  | Name | Value
C_BAUDRATE | 115200
C_DATA_BITS | 8
C_USE_PARITY | 0
C_ODD_PARITY | 1
C_S_AXI_PROTOCOL | AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
mbref_mio_0 axi_mbref_mio MicroBlaze References simple memory bank for AXI4.
IP Specs
Core | Version
axi_mbref_mio | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_ID_WIDTH | 4
C_RDATA_FIFO_DEPTH | 0
C_INCLUDE_TIMEOUT_CNT | 1
C_TIMEOUT_CNTR_VAL | 8
C_ALIGN_BE_RDADDR | 0
C_S_AXI_SUPPORTS_WRITE | 1
C_S_AXI_SUPPORTS_READ | 1
C_FAMILY | virtex6 |  | Name | Value
C_S_AXI_MEM0_BASEADDR | 0x80410000
C_S_AXI_MEM0_HIGHADDR | 0x80410FFF
C_S_AXI_MEM1_BASEADDR | 0x80411000
C_S_AXI_MEM1_HIGHADDR | 0x80411FFF
C_S_AXI_MEM2_BASEADDR | 0x80412000
C_S_AXI_MEM2_HIGHADDR | 0x80412FFF
C_S_AXI_MEM3_BASEADDR | 0x80413000
C_S_AXI_MEM3_HIGHADDR | 0x80413FFF
C_S_AXI_PROTOCOL | AXI4
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
mbref_reg_0 axi_mbref_reg MicroBlaze References simple register bank for AXI4 Lite.
IP Specs
Core | Version
axi_mbref_reg | 1.00.a
| PORT LIST
These are the ports listed in the MHS file.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_50_0000MHzMMCM0
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 15 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_MIN_SIZE | 0x000001FF
C_USE_WSTRB | 0
C_DPHASE_TIMEOUT | 8
C_BASEADDR | 0x80800000
C_HIGHADDR | 0x8080FFFF |  | Name | Value
C_FAMILY | virtex6
C_NUM_REG | 1
C_NUM_MEM | 1
C_SLV_AWIDTH | 32
C_SLV_DWIDTH | 32
C_S_AXI_PROTOCOL | AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
IP | TOC
axi_emc_0_CE_inverter Utility Vector Logic 'Simple logic functions, and, or, xor, not.'
IP Specs
Core | Version | Documentation
util_vector_logic | 1.00.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | Op1 | I | 1 | fpga_0_axi_emc_0_Mem_CEN_invertor_Op1_Adhoc
1 | Res | O | 1 | fpga_0_axi_emc_0_CE_inverter_Res_pin
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_OPERATION | not
C_SIZE | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
clock_generator_0 Clock Generator Clock generator for processor system.
IP Specs
Core | Version | Documentation
clock_generator | 4.03.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | RST | I | 1 | sys_rst_s
1 | CLKIN | I | 1 | dcm_clk_s
2 | CLKOUT0 | O | 1 | clk_100_0000MHzMMCM0
3 | CLKOUT1 | O | 1 | clk_200_0000MHzMMCM0
4 | CLKOUT2 | O | 1 | clk_400_0000MHzMMCM0
5 | CLKOUT3 | O | 1 | clk_400_0000MHzMMCM0_nobuf_varphase
6 | CLKOUT4 | O | 1 | clk_50_0000MHzMMCM0
7 | LOCKED | O | 1 | proc_sys_reset_0_Dcm_locked
8 | PSCLK | I | 1 | clk_100_0000MHzMMCM0
9 | PSEN | I | 1 | psen
10 | PSINCDEC | I | 1 | psincdec
11 | PSDONE | O | 1 | psdone
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_DEVICE | NOT_SET
C_PACKAGE | NOT_SET
C_SPEEDGRADE | NOT_SET
C_CLKIN_FREQ | 200000000
C_CLKOUT0_FREQ | 100000000
C_CLKOUT0_PHASE | 0
C_CLKOUT0_GROUP | MMCM0
C_CLKOUT0_BUF | TRUE
C_CLKOUT0_VARIABLE_PHASE | FALSE
C_CLKOUT1_FREQ | 200000000
C_CLKOUT1_PHASE | 0
C_CLKOUT1_GROUP | MMCM0
C_CLKOUT1_BUF | TRUE
C_CLKOUT1_VARIABLE_PHASE | FALSE
C_CLKOUT2_FREQ | 400000000
C_CLKOUT2_PHASE | 0
C_CLKOUT2_GROUP | MMCM0
C_CLKOUT2_BUF | TRUE
C_CLKOUT2_VARIABLE_PHASE | FALSE
C_CLKOUT3_FREQ | 400000000
C_CLKOUT3_PHASE | 0
C_CLKOUT3_GROUP | MMCM0
C_CLKOUT3_BUF | FALSE
C_CLKOUT3_VARIABLE_PHASE | TRUE
C_CLKOUT4_FREQ | 50000000
C_CLKOUT4_PHASE | 0
C_CLKOUT4_GROUP | MMCM0
C_CLKOUT4_BUF | TRUE
C_CLKOUT4_VARIABLE_PHASE | FALSE
C_CLKOUT5_FREQ | 0
C_CLKOUT5_PHASE | 0
C_CLKOUT5_GROUP | NONE
C_CLKOUT5_BUF | TRUE
C_CLKOUT5_VARIABLE_PHASE | FALSE
C_CLKOUT6_FREQ | 0
C_CLKOUT6_PHASE | 0
C_CLKOUT6_GROUP | NONE
C_CLKOUT6_BUF | TRUE
C_CLKOUT6_VARIABLE_PHASE | FALSE
C_CLKOUT7_FREQ | 0
C_CLKOUT7_PHASE | 0
C_CLKOUT7_GROUP | NONE
C_CLKOUT7_BUF | TRUE
C_CLKOUT7_VARIABLE_PHASE | FALSE
C_CLKOUT8_FREQ | 0
C_CLKOUT8_PHASE | 0
C_CLKOUT8_GROUP | NONE
C_CLKOUT8_BUF | TRUE
C_CLKOUT8_VARIABLE_PHASE | FALSE
C_CLKOUT9_FREQ | 0
C_CLKOUT9_PHASE | 0
C_CLKOUT9_GROUP | NONE
C_CLKOUT9_BUF | TRUE
C_CLKOUT9_VARIABLE_PHASE | FALSE
C_CLKOUT10_FREQ | 0 |  | Name | Value
C_CLKOUT10_PHASE | 0
C_CLKOUT10_GROUP | NONE
C_CLKOUT10_BUF | TRUE
C_CLKOUT10_VARIABLE_PHASE | FALSE
C_CLKOUT11_FREQ | 0
C_CLKOUT11_PHASE | 0
C_CLKOUT11_GROUP | NONE
C_CLKOUT11_BUF | TRUE
C_CLKOUT11_VARIABLE_PHASE | FALSE
C_CLKOUT12_FREQ | 0
C_CLKOUT12_PHASE | 0
C_CLKOUT12_GROUP | NONE
C_CLKOUT12_BUF | TRUE
C_CLKOUT12_VARIABLE_PHASE | FALSE
C_CLKOUT13_FREQ | 0
C_CLKOUT13_PHASE | 0
C_CLKOUT13_GROUP | NONE
C_CLKOUT13_BUF | TRUE
C_CLKOUT13_VARIABLE_PHASE | FALSE
C_CLKOUT14_FREQ | 0
C_CLKOUT14_PHASE | 0
C_CLKOUT14_GROUP | NONE
C_CLKOUT14_BUF | TRUE
C_CLKOUT14_VARIABLE_PHASE | FALSE
C_CLKOUT15_FREQ | 0
C_CLKOUT15_PHASE | 0
C_CLKOUT15_GROUP | NONE
C_CLKOUT15_BUF | TRUE
C_CLKOUT15_VARIABLE_PHASE | FALSE
C_CLKFBIN_FREQ | 0
C_CLKFBIN_DESKEW | NONE
C_CLKFBOUT_FREQ | 0
C_CLKFBOUT_PHASE | 0
C_CLKFBOUT_GROUP | NONE
C_CLKFBOUT_BUF | TRUE
C_PSDONE_GROUP | NONE
C_EXT_RESET_HIGH | 1
C_CLK_PRIMITIVE_FEEDBACK_BUF | FALSE
C_CLKOUT0_DUTY_CYCLE | 0.500000
C_CLKOUT1_DUTY_CYCLE | 0.500000
C_CLKOUT2_DUTY_CYCLE | 0.500000
C_CLKOUT3_DUTY_CYCLE | 0.500000
C_CLKOUT4_DUTY_CYCLE | 0.500000
C_CLKOUT5_DUTY_CYCLE | 0.500000
C_CLKOUT6_DUTY_CYCLE | 0.500000
C_CLKOUT7_DUTY_CYCLE | 0.500000
C_CLKOUT8_DUTY_CYCLE | 0.500000
C_CLKOUT9_DUTY_CYCLE | 0.500000
C_CLKOUT10_DUTY_CYCLE | 0.500000
C_CLKOUT11_DUTY_CYCLE | 0.500000
C_CLKOUT12_DUTY_CYCLE | 0.500000
C_CLKOUT13_DUTY_CYCLE | 0.500000
C_CLKOUT14_DUTY_CYCLE | 0.500000
C_CLKOUT15_DUTY_CYCLE | 0.500000
C_CLK_GEN | UPDATE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
proc_sys_reset_0 Processor System Reset Module Reset management module
IP Specs
Core | Version | Documentation
proc_sys_reset | 3.00.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | Ext_Reset_In | I | 1 | sys_rst_s
1 | MB_Reset | O | 1 | proc_sys_reset_0_MB_Reset
2 | Slowest_sync_clk | I | 1 | clk_50_0000MHzMMCM0
3 | Interconnect_aresetn | O | 1 | proc_sys_reset_0_Interconnect_aresetn
4 | Dcm_locked | I | 1 | proc_sys_reset_0_Dcm_locked
5 | MB_Debug_Sys_Rst | I | 1 | proc_sys_reset_0_MB_Debug_Sys_Rst
6 | BUS_STRUCT_RESET | O | 1 | proc_sys_reset_0_BUS_STRUCT_RESET
7 | Aux_Reset_In | I | 1 | internal_reset_request
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SUBFAMILY | lx
C_EXT_RST_WIDTH | 4
C_AUX_RST_WIDTH | 4
C_EXT_RESET_HIGH | 1
C_AUX_RESET_HIGH | 1
C_NUM_BUS_RST | 1
C_NUM_PERP_RST | 1
C_NUM_INTERCONNECT_ARESETN | 1
C_NUM_PERP_ARESETN | 1
C_FAMILY | virtex5 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Timing Information | TOC Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.