
<EDKSYSTEM EDKVERSION="13.4" EDWVERSION="1.2" TIMESTAMP="Wed Jan 22 19:51:30 2014">

  <SYSTEMINFO ARCH="virtex6" DEVICE="xc6vlx240t" PACKAGE="ff1156" PART="xc6vlx240tff1156-1" SOURCE="/var/lib/jenkins/workspace/build-mbref-xilinx-ml605-mmu/BOARD/Xilinx-ML605-MMU/ISE/13.4/LABEL/linux32/LAYOUT/full/mbref-2014.03-14432/working-designs/Xilinx-ML605-MMU-full-13.4/system.xmp" SPEEDGRADE="-1"/>

  <EXTERNALPORTS>
    <PORT DIR="IO" MHS_INDEX="0" NAME="fpga_0_xps_iic_0_Sda_pin" SIGNAME="fpga_0_xps_iic_0_Sda_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="xps_iic_0" PORT="Sda"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="1" NAME="fpga_0_xps_iic_0_Scl_pin" SIGNAME="fpga_0_xps_iic_0_Scl_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="xps_iic_0" PORT="Scl"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="7" MHS_INDEX="2" MSB="0" NAME="fpga_0_xps_gpio_3_GPIO_IO_pin" RIGHT="7" SIGNAME="fpga_0_xps_gpio_3_GPIO_IO_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="xps_gpio_3" PORT="GPIO_IO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="4" MHS_INDEX="3" MSB="0" NAME="fpga_0_xps_gpio_4_GPIO_IO_pin" RIGHT="4" SIGNAME="fpga_0_xps_gpio_4_GPIO_IO_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="xps_gpio_4" PORT="GPIO_IO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="4" MHS_INDEX="4" MSB="0" NAME="fpga_0_xps_gpio_1_GPIO_IO_pin" RIGHT="4" SIGNAME="fpga_0_xps_gpio_1_GPIO_IO_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="xps_gpio_1" PORT="GPIO_IO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="7" MHS_INDEX="5" MSB="0" NAME="fpga_0_xps_gpio_2_GPIO_IO_pin" RIGHT="7" SIGNAME="fpga_0_xps_gpio_2_GPIO_IO_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="xps_gpio_2" PORT="GPIO_IO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="BIG" LEFT="7" LSB="30" MHS_INDEX="6" MSB="7" NAME="fpga_0_xps_mch_emc_0_Mem_A_pin" RIGHT="30" SIGNAME="fpga_0_xps_mch_emc_0_Mem_A_pin_vslice_7_30_concat">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[emc_0]" INSTANCE="xps_mch_emc_0" PORT="Mem_A"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="7" NAME="fpga_0_xps_mch_emc_0_Mem_OEN_pin" SIGNAME="fpga_0_xps_mch_emc_0_Mem_OEN_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[emc_0]" INSTANCE="xps_mch_emc_0" PORT="Mem_OEN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="8" NAME="fpga_0_xps_mch_emc_0_Mem_WEN_pin" SIGNAME="fpga_0_xps_mch_emc_0_Mem_WEN_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[emc_0]" INSTANCE="xps_mch_emc_0" PORT="Mem_WEN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="15" MHS_INDEX="9" MSB="0" NAME="fpga_0_xps_mch_emc_0_Mem_DQ_pin" RIGHT="15" SIGNAME="fpga_0_xps_mch_emc_0_Mem_DQ_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[emc_0]" INSTANCE="xps_mch_emc_0" PORT="Mem_DQ"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="10" NAME="fpga_0_PCIe_Bridge_RXN_pin" SIGNAME="fpga_0_PCIe_Bridge_RXN_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[pcie_0]" INSTANCE="PCIe_Bridge" PORT="RXN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="11" NAME="fpga_0_PCIe_Bridge_RXP_pin" SIGNAME="fpga_0_PCIe_Bridge_RXP_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[pcie_0]" INSTANCE="PCIe_Bridge" PORT="RXP"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="12" NAME="fpga_0_PCIe_Bridge_TXN_pin" SIGNAME="fpga_0_PCIe_Bridge_TXN_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[pcie_0]" INSTANCE="PCIe_Bridge" PORT="TXN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="13" NAME="fpga_0_PCIe_Bridge_TXP_pin" SIGNAME="fpga_0_PCIe_Bridge_TXP_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[pcie_0]" INSTANCE="PCIe_Bridge" PORT="TXP"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="14" NAME="fpga_0_mpmc_0_DDR3_Clk_pin" SIGIS="CLK" SIGNAME="fpga_0_mpmc_0_DDR3_Clk_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_Clk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="15" NAME="fpga_0_mpmc_0_DDR3_Clk_n_pin" SIGIS="CLK" SIGNAME="fpga_0_mpmc_0_DDR3_Clk_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_Clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="16" NAME="fpga_0_mpmc_0_DDR3_CE_pin" SIGNAME="fpga_0_mpmc_0_DDR3_CE_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_CE"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="17" NAME="fpga_0_mpmc_0_DDR3_CS_n_pin" SIGNAME="fpga_0_mpmc_0_DDR3_CS_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_CS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="18" NAME="fpga_0_mpmc_0_DDR3_ODT_pin" SIGNAME="fpga_0_mpmc_0_DDR3_ODT_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_ODT"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="19" NAME="fpga_0_mpmc_0_DDR3_RAS_n_pin" SIGNAME="fpga_0_mpmc_0_DDR3_RAS_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_RAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="20" NAME="fpga_0_mpmc_0_DDR3_CAS_n_pin" SIGNAME="fpga_0_mpmc_0_DDR3_CAS_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_CAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="21" NAME="fpga_0_mpmc_0_DDR3_WE_n_pin" SIGNAME="fpga_0_mpmc_0_DDR3_WE_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_WE_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="22" MSB="2" NAME="fpga_0_mpmc_0_DDR3_BankAddr_pin" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_BankAddr_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_BankAddr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="23" MSB="12" NAME="fpga_0_mpmc_0_DDR3_Addr_pin" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_Addr_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_Addr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="24" MSB="31" NAME="fpga_0_mpmc_0_DDR3_DQ_pin" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DQ_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_DQ"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="25" MSB="3" NAME="fpga_0_mpmc_0_DDR3_DM_pin" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DM_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_DM"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="26" NAME="fpga_0_mpmc_0_DDR3_Reset_n_pin" SIGNAME="fpga_0_mpmc_0_DDR3_Reset_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_Reset_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="27" MSB="3" NAME="fpga_0_mpmc_0_DDR3_DQS_pin" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DQS_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_DQS"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="28" MSB="3" NAME="fpga_0_mpmc_0_DDR3_DQS_n_pin" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DQS_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[memory_0]" INSTANCE="mpmc_0" PORT="DDR3_DQS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MHS_INDEX="29" MSB="6" NAME="fpga_0_xps_sysace_0_SysACE_MPA_pin" RIGHT="0" SIGNAME="fpga_0_xps_sysace_0_SysACE_MPA_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[sysace_0]" INSTANCE="xps_sysace_0" PORT="SysACE_MPA"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="30" NAME="fpga_0_xps_sysace_0_SysACE_CLK_pin" SIGNAME="fpga_0_xps_sysace_0_SysACE_CLK_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[sysace_0]" INSTANCE="xps_sysace_0" PORT="SysACE_CLK"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="31" NAME="fpga_0_xps_sysace_0_SysACE_MPIRQ_pin" SIGNAME="fpga_0_xps_sysace_0_SysACE_MPIRQ_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[sysace_0]" INSTANCE="xps_sysace_0" PORT="SysACE_MPIRQ"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="32" NAME="fpga_0_xps_sysace_0_SysACE_CEN_pin" SIGNAME="fpga_0_xps_sysace_0_SysACE_CEN_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[sysace_0]" INSTANCE="xps_sysace_0" PORT="SysACE_CEN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="33" NAME="fpga_0_xps_sysace_0_SysACE_OEN_pin" SIGNAME="fpga_0_xps_sysace_0_SysACE_OEN_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[sysace_0]" INSTANCE="xps_sysace_0" PORT="SysACE_OEN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="34" NAME="fpga_0_xps_sysace_0_SysACE_WEN_pin" SIGNAME="fpga_0_xps_sysace_0_SysACE_WEN_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[sysace_0]" INSTANCE="xps_sysace_0" PORT="SysACE_WEN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="35" MSB="7" NAME="fpga_0_xps_sysace_0_SysACE_MPD_pin" RIGHT="0" SIGNAME="fpga_0_xps_sysace_0_SysACE_MPD_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[sysace_0]" INSTANCE="xps_sysace_0" PORT="SysACE_MPD"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="36" NAME="fpga_0_xps_ether_0_TemacPhy_RST_n_pin" SIGNAME="fpga_0_xps_ether_0_TemacPhy_RST_n_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="TemacPhy_RST_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="37" NAME="fpga_0_xps_ether_0_MII_TX_CLK_0_pin" SIGNAME="fpga_0_xps_ether_0_MII_TX_CLK_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="MII_TX_CLK_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="38" MSB="7" NAME="fpga_0_xps_ether_0_GMII_TXD_0_pin" RIGHT="0" SIGNAME="fpga_0_xps_ether_0_GMII_TXD_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_TXD_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="39" NAME="fpga_0_xps_ether_0_GMII_TX_EN_0_pin" SIGNAME="fpga_0_xps_ether_0_GMII_TX_EN_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_TX_EN_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="40" NAME="fpga_0_xps_ether_0_GMII_TX_ER_0_pin" SIGNAME="fpga_0_xps_ether_0_GMII_TX_ER_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_TX_ER_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="41" NAME="fpga_0_xps_ether_0_GMII_TX_CLK_0_pin" SIGNAME="fpga_0_xps_ether_0_GMII_TX_CLK_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_TX_CLK_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="42" MSB="7" NAME="fpga_0_xps_ether_0_GMII_RXD_0_pin" RIGHT="0" SIGNAME="fpga_0_xps_ether_0_GMII_RXD_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_RXD_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="43" NAME="fpga_0_xps_ether_0_GMII_RX_DV_0_pin" SIGNAME="fpga_0_xps_ether_0_GMII_RX_DV_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_RX_DV_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="44" NAME="fpga_0_xps_ether_0_GMII_RX_ER_0_pin" SIGNAME="fpga_0_xps_ether_0_GMII_RX_ER_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_RX_ER_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="45" NAME="fpga_0_xps_ether_0_GMII_RX_CLK_0_pin" SIGNAME="fpga_0_xps_ether_0_GMII_RX_CLK_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GMII_RX_CLK_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="46" NAME="fpga_0_xps_ether_0_MDC_0_pin" SIGNAME="fpga_0_xps_ether_0_MDC_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="MDC_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="47" NAME="fpga_0_xps_ether_0_MDIO_0_pin" SIGNAME="fpga_0_xps_ether_0_MDIO_0_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="MDIO_0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="48" NAME="fpga_0_xps_uart_0_sin_pin" SIGNAME="fpga_0_xps_uart_0_sin_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[uart_0]" INSTANCE="xps_uart_0" PORT="sin"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="49" NAME="fpga_0_xps_uart_0_sout_pin" SIGNAME="fpga_0_xps_uart_0_sout_pin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[uart_0]" INSTANCE="xps_uart_0" PORT="sout"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="50" NAME="fpga_0_clk_1_sys_clk_p_pin" SIGIS="CLK" SIGNAME="dcm_clk_s">
      <CONNECTIONS>
        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="51" NAME="fpga_0_clk_1_sys_clk_n_pin" SIGIS="CLK" SIGNAME="dcm_clk_s">
      <CONNECTIONS>
        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="52" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="1" SIGIS="RST" SIGNAME="sys_rst_s">
      <CONNECTIONS>
        <CONNECTION INSTANCE="clock_generator_0" PORT="RST"/>
        <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Ext_Reset_In"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="53" NAME="fpga_0_xps_mch_emc_0_CE_inverter_Res_pin" SIGNAME="fpga_0_xps_mch_emc_0_CE_inverter_Res_pin">
      <CONNECTIONS>
        <CONNECTION INSTANCE="xps_mch_emc_0_CE_inverter" PORT="Res"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="54" NAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" SIGNAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin">
      <CONNECTIONS>
        <CONNECTION INSTANCE="PCIe_Diff_Clk" PORT="IBUF_DS_P"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="55" NAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" SIGNAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin">
      <CONNECTIONS>
        <CONNECTION INSTANCE="PCIe_Diff_Clk" PORT="IBUF_DS_N"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <MODULES>
    <MODULE HWVERSION="8.20.b" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="0" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
      <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_20_b/doc/microblaze.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
        <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="virtex6"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
        <PARAMETER MPD_INDEX="6" NAME="C_AVOID_PRIMITIVES" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="7" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="9" NAME="C_LOCKSTEP_SLAVE" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="10" NAME="C_ENDIANNESS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="11" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0">
          <DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="13" NAME="C_INTERCONNECT" TYPE="integer" VALUE="1">
          <DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0">
          <DESCRIPTION>Select Stream Interfaces</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="15" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="64"/>
        <PARAMETER MPD_INDEX="16" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="17" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="18" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="64"/>
        <PARAMETER MPD_INDEX="20" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="21" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="22" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="30" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
        <PARAMETER MPD_INDEX="31" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="32" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="33" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="40" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="41" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
        <PARAMETER MPD_INDEX="42" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="43" NAME="C_D_AXI" TYPE="integer" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="44" NAME="C_D_PLB" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="45" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="46" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="47" NAME="C_I_PLB" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="48" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="49" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="51" NAME="C_USE_BARREL" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="52" NAME="C_USE_DIV" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Integer Divider</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="53" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="54" NAME="C_USE_FPU" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="55" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="56" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="58" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="59" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="60" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="61" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="62" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="63" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Stream Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="64" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>&lt;qt&gt;Enable stack protection&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="28" MPD_INDEX="65" NAME="C_PVR" TYPE="integer" VALUE="2">
          <DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="66" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
          <DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="67" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="68" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="69" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="70" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="71" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="72" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="73" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
          <DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="74" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="75" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="1">
          <DESCRIPTION>&lt;qt&gt;Generate Illegal Instruction Exception for NULL Instruction&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="76" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of Stream Links </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="77" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="78" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="79" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="80" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="81" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="82" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="83" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="84" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="85" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="86" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="87" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="88" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="89" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="90" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="91" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="92" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="93" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="94" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="95" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="96" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="97" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="98" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="99" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="100" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="101" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="102" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="103" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="104" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="105" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="106" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="107" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="108" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="109" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="110" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
        <PARAMETER MPD_INDEX="111" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="112" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="113" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="114" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="115" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="116" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="117" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="118" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="119" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="120" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="121" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="122" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="123" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="124" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="125" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="126" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="127" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="128" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="129" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="130" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="131" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="132" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="133" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="134" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="135" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="136" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="137" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="138" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="139" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="140" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="141" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="142" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="143" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x20000000">
          <DESCRIPTION>Base Address </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="144" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x2fffffff">
          <DESCRIPTION>High Address </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="145" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="146" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Writes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="14"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="148" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
          <DESCRIPTION>Size in Bytes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="149" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="150" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="8">
          <DESCRIPTION>Line Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="151" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
          <DESCRIPTION>Use Cache Links for All Memory Accesses </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="152" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="25" MPD_INDEX="153" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="8">
          <DESCRIPTION>Number of Victims</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="154" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Streams</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="155" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
          <DESCRIPTION>Use Distributed RAM for Tags</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="156" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0">
          <DESCRIPTION>Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
        <PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
        <PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
        <PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
        <PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="170" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="171" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="172" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="173" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x20000000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="174" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x2fffffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="175" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Data Cache</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="176" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Writes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="14"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="178" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="16384">
          <DESCRIPTION>Size in Bytes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="179" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="180" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4">
          <DESCRIPTION>Line Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="181" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
          <DESCRIPTION>Use Cache Links for All Memory Accesses </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="182" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="183" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="184" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of Victims</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="185" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0">
          <DESCRIPTION>Use Distributed RAM for Tags</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="186" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0">
          <DESCRIPTION>Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
        <PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
        <PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
        <PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
        <PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="201" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="202" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="203" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
        <PARAMETER MPD_INDEX="204" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="205" NAME="C_USE_MMU" TYPE="integer" VALUE="3">
          <DESCRIPTION>Memory Management</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="206" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4">
          <DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="207" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
          <DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="208" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
          <DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="209" NAME="C_MMU_ZONES" TYPE="integer" VALUE="2">
          <DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="210" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0">
          <DESCRIPTION>Privileged Instructions</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="212" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="213" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="214" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="215" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="mb_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="MB_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_Interrupt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Irq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB:ILMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="dlmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mdm_0" PORT="Ext_BRK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mdm_0" PORT="Ext_NM_BRK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="4095" MPD_INDEX="9" MSB="0" NAME="LOCKSTEP_MASTER_OUT" RIGHT="4095" SIGNAME="__NOC__" VECFORMULA="[0:4095]"/>
        <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="4095" MPD_INDEX="10" MSB="0" NAME="LOCKSTEP_SLAVE_IN" RIGHT="4095" SIGNAME="__NOC__" VECFORMULA="[0:4095]"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="4095" MPD_INDEX="11" MSB="0" NAME="LOCKSTEP_OUT" RIGHT="4095" SIGNAME="__NOC__" VECFORMULA="[0:4095]"/>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_READDBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Ready" DIR="I" MPD_INDEX="13" NAME="IREADY" SIGNAME="ilmb_LMB_Ready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_READY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Wait" DIR="I" MPD_INDEX="14" NAME="IWAIT" SIGNAME="ilmb_LMB_Wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_WAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_CE" DIR="I" MPD_INDEX="15" NAME="ICE" SIGNAME="ilmb_LMB_CE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_UE" DIR="I" MPD_INDEX="16" NAME="IUE" SIGNAME="ilmb_LMB_UE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="M_ABUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="18" NAME="IFETCH" SIGNAME="ilmb_M_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="M_READSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="19" NAME="I_AS" SIGNAME="ilmb_M_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="M_ADDRSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="20" NAME="IPLB_M_ABort" SIGNAME="mb_plb_M_ABort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="22" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="23" MSB="0" NAME="IPLB_M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="24" NAME="IPLB_M_busLock" SIGNAME="mb_plb_M_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="25" NAME="IPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_priority"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="28" NAME="IPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="29" NAME="IPLB_M_request" SIGNAME="mb_plb_M_request">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_request"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="30" NAME="IPLB_M_RNW" SIGNAME="mb_plb_M_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="31" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="32" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="33" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="34" NAME="IPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="35" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="36" NAME="IPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="37" NAME="IPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="39" NAME="IPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="40" NAME="IPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="41" NAME="IPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="42" NAME="IPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MAddrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="43" NAME="IPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="44" NAME="IPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="45" MSB="0" NAME="IPLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="47" NAME="IPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="48" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="49" NAME="IPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MTimeout"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_READDBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Ready" DIR="I" MPD_INDEX="51" NAME="DREADY" SIGNAME="dlmb_LMB_Ready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_READY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Wait" DIR="I" MPD_INDEX="52" NAME="DWAIT" SIGNAME="dlmb_LMB_Wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_WAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_CE" DIR="I" MPD_INDEX="53" NAME="DCE" SIGNAME="dlmb_LMB_CE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_UE" DIR="I" MPD_INDEX="54" NAME="DUE" SIGNAME="dlmb_LMB_UE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="55" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="M_DBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="M_ABUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="57" NAME="D_AS" SIGNAME="dlmb_M_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="M_ADDRSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="58" NAME="READ_STROBE" SIGNAME="dlmb_M_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="M_READSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="59" NAME="WRITE_STROBE" SIGNAME="dlmb_M_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="M_WRITESTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="60" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="M_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="61" NAME="DPLB_M_ABort" SIGNAME="mb_plb_M_ABort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="62" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="63" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="DPLB_M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="65" NAME="DPLB_M_busLock" SIGNAME="mb_plb_M_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="66" NAME="DPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="67" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="68" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_priority"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="69" NAME="DPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="70" NAME="DPLB_M_request" SIGNAME="mb_plb_M_request">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_request"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="71" NAME="DPLB_M_RNW" SIGNAME="mb_plb_M_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="72" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="73" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="74" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="75" NAME="DPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="76" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="77" NAME="DPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="78" NAME="DPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="80" NAME="DPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="81" NAME="DPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="82" NAME="DPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="83" NAME="DPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MAddrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="84" NAME="DPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="85" NAME="DPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="86" MSB="0" NAME="DPLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="87" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="88" NAME="DPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="89" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="90" NAME="DPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MTimeout"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="92" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="93" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="94" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="95" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="97" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="98" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="101" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="102" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="103" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="112" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="114" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="115" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="116" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="117" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="118" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="119" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="121" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="124" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="M_AXI_DP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="129" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="131" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="132" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="133" NAME="M_AXI_DP_AWLOCK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="134" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="136" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="M_AXI_DP_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="138" NAME="M_AXI_DP_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="139" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="M_AXI_DP_WLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="M_AXI_DP_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="M_AXI_DP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="146" NAME="M_AXI_DP_BVALID" SIGNAME="__NOC__"/>
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        </PORT>
        <PORT BUS="DXCL" DEF_SIGNAME="microblaze_0_DXCL_FSL_M_Data" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="592" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="microblaze_0_DXCL_FSL_M_Data" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[XCL2]" INSTANCE="mpmc_0" PORT="FSL2_M_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DXCL" DEF_SIGNAME="microblaze_0_DXCL_FSL_M_Control" DIR="O" MPD_INDEX="593" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="microblaze_0_DXCL_FSL_M_Control">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[XCL2]" INSTANCE="mpmc_0" PORT="FSL2_M_Control"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="DXCL" DEF_SIGNAME="microblaze_0_DXCL_FSL_M_Full" DIR="I" MPD_INDEX="594" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="microblaze_0_DXCL_FSL_M_Full">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[XCL2]" INSTANCE="mpmc_0" PORT="FSL2_M_Full"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
            <PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
            <PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
            <PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="RESET"/>
            <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
            <PORTMAP DIR="I" PHYSICAL="DREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
            <PORTMAP DIR="I" PHYSICAL="DCE"/>
            <PORTMAP DIR="I" PHYSICAL="DUE"/>
            <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
            <PORTMAP DIR="O" PHYSICAL="D_AS"/>
            <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
            <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
            <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="6" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="RESET"/>
            <PORTMAP DIR="I" PHYSICAL="INSTR"/>
            <PORTMAP DIR="I" PHYSICAL="IREADY"/>
            <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
            <PORTMAP DIR="I" PHYSICAL="ICE"/>
            <PORTMAP DIR="I" PHYSICAL="IUE"/>
            <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
            <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
            <PORTMAP DIR="O" PHYSICAL="I_AS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_mdm_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
            <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
            <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_IXCL" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="3" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_DXCL" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="dlmb_cntlr" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="dlmb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" INSTANCE="ilmb_cntlr" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="8192" SIZEABRV="8K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="ilmb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2163998720" BASENAME="C_BASEADDR" BASEVALUE="0x80FC0000" HIGHDECIMAL="2164064255" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FCFFFF" INSTANCE="xps_gpio_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2163933184" BASENAME="C_BASEADDR" BASEVALUE="0x80FB0000" HIGHDECIMAL="2163998719" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FBFFFF" INSTANCE="xps_gpio_4" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2164129792" BASENAME="C_BASEADDR" BASEVALUE="0x80FE0000" HIGHDECIMAL="2164195327" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FEFFFF" INSTANCE="xps_gpio_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2164064256" BASENAME="C_BASEADDR" BASEVALUE="0x80FD0000" HIGHDECIMAL="2164129791" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FDFFFF" INSTANCE="xps_gpio_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2919235584" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0xAE000000" HIGHDECIMAL="2952790015" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0xAFFFFFFF" INSTANCE="xps_mch_emc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="33554432" SIZEABRV="32M">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2327773184" BASENAME="C_BASEADDR" BASEVALUE="0x8ABF0000" HIGHDECIMAL="2327838719" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8ABFFFFF" INSTANCE="PCIe_Bridge" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2952790016" BASENAME="C_IPIFBAR_0" BASEVALUE="0xB0000000" HIGHDECIMAL="2969567231" HIGHNAME="C_IPIFBAR_HIGHADDR_0" HIGHVALUE="0xB0FFFFFF" INSTANCE="PCIe_Bridge" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="BRIDGE" SIZE="16777216" SIZEABRV="16M">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_IPIFBAR_1" BASEVALUE="0xe0000000" HIGHDECIMAL="4294967295" HIGHNAME="C_IPIFBAR_HIGHADDR_1" HIGHVALUE="0xffffffff" INSTANCE="PCIe_Bridge" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="BRIDGE" SIZE="536870912" SIZEABRV="512M">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_IPIFBAR_2" BASEVALUE="0xc0000000" HIGHDECIMAL="3489660927" HIGHNAME="C_IPIFBAR_HIGHADDR_2" HIGHVALUE="0xcfffffff" INSTANCE="PCIe_Bridge" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="BRIDGE" SIZE="268435456" SIZEABRV="256M">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="536870912" BASENAME="C_MPMC_BASEADDR" BASEVALUE="0x20000000" HIGHDECIMAL="805306367" HIGHNAME="C_MPMC_HIGHADDR" HIGHVALUE="0x2FFFFFFF" INSTANCE="mpmc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="268435456" SIZEABRV="256M">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_DXCL"/>
          </ACCESSROUTE>
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_IXCL"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2329870336" BASENAME="C_SDMA_CTRL_BASEADDR" BASEVALUE="0x8ADF0000" HIGHDECIMAL="2329935871" HIGHNAME="C_SDMA_CTRL_HIGHADDR" HIGHVALUE="0x8ADFFFFF" INSTANCE="mpmc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2204106752" BASENAME="C_BASEADDR" BASEVALUE="0x83600000" HIGHDECIMAL="2204172287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8360ffff" INSTANCE="xps_sysace_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2297430016" BASENAME="C_BASEADDR" BASEVALUE="0x88F00000" HIGHDECIMAL="2297954303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x88F7FFFF" INSTANCE="xps_ether_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="524288" SIZEABRV="512K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2330918912" BASENAME="C_BASEADDR" BASEVALUE="0x8AEF0000" HIGHDECIMAL="2330984447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8AEFFFFF" INSTANCE="xps_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2315190272" BASENAME="C_BASEADDR" BASEVALUE="0x89FF0000" HIGHDECIMAL="2315255807" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x89FFFFFF" INSTANCE="xps_uart_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2328821760" BASENAME="C_BASEADDR" BASEVALUE="0x8ACF0000" HIGHDECIMAL="2328887295" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8ACFFFFF" INSTANCE="xps_central_dma_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2415853568" BASENAME="C_BASEADDR" BASEVALUE="0x8FFF0000" HIGHDECIMAL="2415919103" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8FFFFFFF" INSTANCE="mdm_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2331967488" BASENAME="C_BASEADDR" BASEVALUE="0x8AFF0000" HIGHDECIMAL="2332033023" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8AFFFFFF" INSTANCE="xps_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2164195328" BASENAME="C_BASEADDR" BASEVALUE="0x80FF0000" HIGHDECIMAL="2164260863" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FFFFFF" INSTANCE="xps_gpio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2163146752" BASENAME="C_BASEADDR" BASEVALUE="0x80EF0000" HIGHDECIMAL="2163212287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80EFFFFF" INSTANCE="xps_iic_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2155872256" BASENAME="C_BASEADDR" BASEVALUE="0x80800000" HIGHDECIMAL="2155937791" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8080FFFF" INSTANCE="mbref_reg_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151677952" BASENAME="C_BASEADDR" BASEVALUE="0x80400000" HIGHDECIMAL="2151743487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8040FFFF" INSTANCE="mbref_mio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151743488" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0x80410000" HIGHDECIMAL="2151743999" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0x804101FF" INSTANCE="mbref_mio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151747584" BASENAME="C_MEM1_BASEADDR" BASEVALUE="0x80411000" HIGHDECIMAL="2151748095" HIGHNAME="C_MEM1_HIGHADDR" HIGHVALUE="0x804111FF" INSTANCE="mbref_mio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151751680" BASENAME="C_MEM2_BASEADDR" BASEVALUE="0x80412000" HIGHDECIMAL="2151752191" HIGHNAME="C_MEM2_HIGHADDR" HIGHVALUE="0x804121FF" INSTANCE="mbref_mio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151755776" BASENAME="C_MEM3_BASEADDR" BASEVALUE="0x80413000" HIGHDECIMAL="2151756287" HIGHNAME="C_MEM3_HIGHADDR" HIGHVALUE="0x804131FF" INSTANCE="mbref_mio_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="dlmb_cntlr"/>
        <PERIPHERAL INSTANCE="ilmb_cntlr"/>
        <PERIPHERAL INSTANCE="xps_gpio_3"/>
        <PERIPHERAL INSTANCE="xps_gpio_4"/>
        <PERIPHERAL INSTANCE="xps_gpio_1"/>
        <PERIPHERAL INSTANCE="xps_gpio_2"/>
        <PERIPHERAL INSTANCE="xps_mch_emc_0"/>
        <PERIPHERAL INSTANCE="PCIe_Bridge"/>
        <PERIPHERAL INSTANCE="mpmc_0"/>
        <PERIPHERAL INSTANCE="xps_sysace_0"/>
        <PERIPHERAL INSTANCE="xps_ether_0"/>
        <PERIPHERAL INSTANCE="xps_timer_0"/>
        <PERIPHERAL INSTANCE="xps_uart_0"/>
        <PERIPHERAL INSTANCE="xps_central_dma_0"/>
        <PERIPHERAL INSTANCE="mdm_0"/>
        <PERIPHERAL INSTANCE="xps_intc_0"/>
        <PERIPHERAL INSTANCE="xps_gpio_0"/>
        <PERIPHERAL INSTANCE="xps_iic_0"/>
        <PERIPHERAL INSTANCE="mbref_reg_0"/>
        <PERIPHERAL INSTANCE="mbref_mio_0"/>
      </PERIPHERALS>
      <INTERRUPTINFO TYPE="TARGET">
        <SOURCE INSTANCE="xps_intc_0" INTC_INDEX="0"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" HWVERSION="1.05.a" INSTANCE="mb_plb" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="plb_v46">
      <DESCRIPTION TYPE="SHORT">Processor Local Bus (PLB) 4.6</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_05_a/doc/plb_v46.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_PLBV46_NUM_MASTERS" TYPE="integer" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="19">
          <DESCRIPTION>Number of PLB Slaves</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_PLBV46_MID_WIDTH" TYPE="integer" VALUE="2">
          <DESCRIPTION>PLB Master ID Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_PLBV46_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_PLBV46_DWIDTH" TYPE="integer" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_DCR_INTFCE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Include DCR Interface and Error Registers</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0b1111111111">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0b0000000000">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_DCR_AWIDTH" TYPE="integer" VALUE="10">
          <DESCRIPTION>DCR Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_DCR_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>DCR Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
          <DESCRIPTION>External Reset Active High </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>IRQ Active State </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_NUM_CLK_PLB2OPB_REARB" TYPE="integer" VALUE="5">
          <DESCRIPTION>&lt;qt&gt;Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_ADDR_PIPELINING_TYPE" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Address Pipelining Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_FAMILY" TYPE="string" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_P2P" TYPE="integer" VALUE="0">
          <DESCRIPTION>Optimize PLB for Point-to-point Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_ARB_TYPE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Selects the Arbitration Scheme</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="sys_bus_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Bus_Struct_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_Rst" DIR="O" MPD_INDEX="2" NAME="PLB_Rst" SIGIS="RST" SIGNAME="mb_plb_PLB_Rst">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="3" MSB="0" NAME="SPLB_Rst" RIGHT="18" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="MCH_SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Rst"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="SPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_MPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="4" MSB="0" NAME="MPLB_Rst" RIGHT="3" SIGIS="RST" SIGNAME="mb_plb_MPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="MPLB_Rst"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="5" NAME="PLB_dcrAck" SIGNAME="__NOC__"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_dcrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="7" MSB="0" NAME="DCR_ABus" RIGHT="9" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_AWIDTH-1]"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="DCR_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="DCR_Read" SIGNAME="__NOC__"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="DCR_Write" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="mb_plb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="11" MSB="0" NAME="M_ABus" RIGHT="127" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_ABus"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_ABus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_ABus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="12" MSB="0" NAME="M_UABus" RIGHT="127" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_UABus"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_UABus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_UABus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="M_BE" RIGHT="31" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_BE"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_BE"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_BE"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_RNW" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="M_RNW" RIGHT="3" SIGNAME="mb_plb_M_RNW" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_RNW"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_RNW"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_RNW"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_abort" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="15" MSB="0" NAME="M_abort" RIGHT="3" SIGNAME="mb_plb_M_abort" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_ABort"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_ABort"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_abort"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_busLock" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="M_busLock" RIGHT="3" SIGNAME="mb_plb_M_busLock" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_busLock"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_busLock"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_buslock"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="M_TAttribute" RIGHT="63" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*16)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_TAttribute"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_TAttribute"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_TAttribute"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_lockErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="M_lockErr" RIGHT="3" SIGNAME="mb_plb_M_lockErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_lockErr"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_lockErr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_lockErr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="19" MSB="0" NAME="M_MSize" RIGHT="7" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_MSize"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_MSize"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_MSize"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_priority" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="20" MSB="0" NAME="M_priority" RIGHT="7" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_priority"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_priority"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_priority"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_priority"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_rdBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="21" MSB="0" NAME="M_rdBurst" RIGHT="3" SIGNAME="mb_plb_M_rdBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_rdBurst"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_rdBurst"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_rdBurst"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_request" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="22" MSB="0" NAME="M_request" RIGHT="3" SIGNAME="mb_plb_M_request" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_request"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_request"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_request"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_request"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="23" MSB="0" NAME="M_size" RIGHT="15" SIGNAME="mb_plb_M_size" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_size"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_size"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_size"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="24" MSB="0" NAME="M_type" RIGHT="11" SIGNAME="mb_plb_M_type" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*3)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_type"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_type"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_type"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_wrBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="M_wrBurst" RIGHT="3" SIGNAME="mb_plb_M_wrBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_wrBurst"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_wrBurst"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_wrBurst"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_M_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="255" MPD_INDEX="26" MSB="0" NAME="M_wrDBus" RIGHT="255" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_M_wrDBus"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_M_wrDBus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="M_wrDBus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="M_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="27" MSB="0" NAME="Sl_addrAck" RIGHT="18" SIGNAME="mb_plb_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_addrAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="75" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="75" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_MRdErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="75" MPD_INDEX="29" MSB="0" NAME="Sl_MWrErr" RIGHT="75" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_MWrErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="I" ENDIAN="BIG" LEFT="0" LSB="75" MPD_INDEX="30" MSB="0" NAME="Sl_MBusy" RIGHT="75" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_MBusy"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="31" MSB="0" NAME="Sl_rdBTerm" RIGHT="18" SIGNAME="mb_plb_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_rdBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="32" MSB="0" NAME="Sl_rdComp" RIGHT="18" SIGNAME="mb_plb_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_rdComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="33" MSB="0" NAME="Sl_rdDAck" RIGHT="18" SIGNAME="mb_plb_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_rdDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1215" MPD_INDEX="34" MSB="0" NAME="Sl_rdDBus" RIGHT="1215" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_rdDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="75" MPD_INDEX="35" MSB="0" NAME="Sl_rdWdAddr" RIGHT="75" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_rdWdAddr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="36" MSB="0" NAME="Sl_rearbitrate" RIGHT="18" SIGNAME="mb_plb_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_rearbitrate"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_SSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="37" MPD_INDEX="37" MSB="0" NAME="Sl_SSize" RIGHT="37" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_SSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_wait" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="38" MSB="0" NAME="Sl_wait" RIGHT="18" SIGNAME="mb_plb_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_wait"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="39" MSB="0" NAME="Sl_wrBTerm" RIGHT="18" SIGNAME="mb_plb_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_wrBTerm"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="40" MSB="0" NAME="Sl_wrComp" RIGHT="18" SIGNAME="mb_plb_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_wrComp"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="41" MSB="0" NAME="Sl_wrDAck" RIGHT="18" SIGNAME="mb_plb_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_wrDAck"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="I" ENDIAN="BIG" LEFT="0" LSB="75" MPD_INDEX="42" MSB="0" NAME="Sl_MIRQ" RIGHT="75" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="Sl_MIRQ"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="PLB_MIRQ" RIGHT="3" SIGNAME="mb_plb_PLB_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MIRQ"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MIRQ"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MIRQ"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="44" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_ABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="45" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_UABus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="46" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:(C_PLBV46_DWIDTH/8)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_BE"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="47" MSB="0" NAME="PLB_MAddrAck" RIGHT="3" SIGNAME="mb_plb_PLB_MAddrAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MAddrAck"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MAddrAck"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MAddrAck"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MAddrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="48" MSB="0" NAME="PLB_MTimeout" RIGHT="3" SIGNAME="mb_plb_PLB_MTimeout" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MTimeout"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MTimeout"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MTimeout"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MTimeout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="49" MSB="0" NAME="PLB_MBusy" RIGHT="3" SIGNAME="mb_plb_PLB_MBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MBusy"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MBusy"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MBusy"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="50" MSB="0" NAME="PLB_MRdErr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MRdErr"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MRdErr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MRdErr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="51" MSB="0" NAME="PLB_MWrErr" RIGHT="3" SIGNAME="mb_plb_PLB_MWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MWrErr"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MWrErr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MWrErr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="52" MSB="0" NAME="PLB_MRdBTerm" RIGHT="3" SIGNAME="mb_plb_PLB_MRdBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MRdBTerm"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MRdBTerm"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MRdBTerm"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MRdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="53" MSB="0" NAME="PLB_MRdDAck" RIGHT="3" SIGNAME="mb_plb_PLB_MRdDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MRdDAck"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MRdDAck"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MRdDAck"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MRdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="255" MPD_INDEX="54" MSB="0" NAME="PLB_MRdDBus" RIGHT="255" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MRdDBus"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MRdDBus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MRdDBus"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MRdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="55" MSB="0" NAME="PLB_MRdWdAddr" RIGHT="15" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MRdWdAddr"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MRdWdAddr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MRdWdAddr"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MRdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="56" MSB="0" NAME="PLB_MRearbitrate" RIGHT="3" SIGNAME="mb_plb_PLB_MRearbitrate" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MRearbitrate"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MRearbitrate"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MRearbitrate"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MRearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="PLB_MWrBTerm" RIGHT="3" SIGNAME="mb_plb_PLB_MWrBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MWrBTerm"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MWrBTerm"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MWrBTerm"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MWrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="PLB_MWrDAck" RIGHT="3" SIGNAME="mb_plb_PLB_MWrDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MWrDAck"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MWrDAck"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MWrDAck"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MWrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="59" MSB="0" NAME="PLB_MSSize" RIGHT="7" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IPLB]" INSTANCE="microblaze_0" PORT="IPLB_MSSize"/>
            <CONNECTION BUSINTERFACE="[DPLB]" INSTANCE="microblaze_0" PORT="DPLB_MSSize"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MSSize"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_MSSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="O" MPD_INDEX="60" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_PAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_RNW" DIR="O" MPD_INDEX="61" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_RNW"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="O" MPD_INDEX="62" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_SAValid"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_abort" DIR="O" MPD_INDEX="63" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_abort"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_busLock" DIR="O" MPD_INDEX="64" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_busLock"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="65" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_TAttribute"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="O" MPD_INDEX="66" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_lockErr"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_masterID" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="67" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:C_PLBV46_MID_WIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_masterID"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="68" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_MSize"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="69" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_rdPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="70" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_wrPendPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_rdPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_wrPendReq"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_rdBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="74" MSB="0" NAME="PLB_rdPrim" RIGHT="18" SIGNAME="mb_plb_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_rdPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="75" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_reqPri"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="76" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_size"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_size"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="77" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_type"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_type"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_wrBurst"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="79" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_wrDBus"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="18" MPD_INDEX="80" MSB="0" NAME="PLB_wrPrim" RIGHT="18" SIGNAME="mb_plb_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="PLB_wrPrim"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SaddrAck" DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="mb_plb_PLB_SaddrAck">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SMRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="82" MSB="0" NAME="PLB_SMRdErr" RIGHT="3" SIGNAME="mb_plb_PLB_SMRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SMWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="83" MSB="0" NAME="PLB_SMWrErr" RIGHT="3" SIGNAME="mb_plb_PLB_SMWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SMBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="84" MSB="0" NAME="PLB_SMBusy" RIGHT="3" SIGNAME="mb_plb_PLB_SMBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdBTerm" DIR="O" MPD_INDEX="85" NAME="PLB_SrdBTerm" SIGNAME="mb_plb_PLB_SrdBTerm">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdComp" DIR="O" MPD_INDEX="86" NAME="PLB_SrdComp" SIGNAME="mb_plb_PLB_SrdComp">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdDAck" DIR="O" MPD_INDEX="87" NAME="PLB_SrdDAck" SIGNAME="mb_plb_PLB_SrdDAck">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="88" MSB="0" NAME="PLB_SrdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_SrdDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="89" MSB="0" NAME="PLB_SrdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_SrdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_Srearbitrate" DIR="O" MPD_INDEX="90" NAME="PLB_Srearbitrate" SIGNAME="mb_plb_PLB_Srearbitrate">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_Sssize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="91" MSB="0" NAME="PLB_Sssize" RIGHT="1" SIGNAME="mb_plb_PLB_Sssize" VECFORMULA="[0:1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_Swait" DIR="O" MPD_INDEX="92" NAME="PLB_Swait" SIGNAME="mb_plb_PLB_Swait">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SwrBTerm" DIR="O" MPD_INDEX="93" NAME="PLB_SwrBTerm" SIGNAME="mb_plb_PLB_SwrBTerm">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SwrComp" DIR="O" MPD_INDEX="94" NAME="PLB_SwrComp" SIGNAME="mb_plb_PLB_SwrComp">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="mb_plb_PLB_SwrDAck" DIR="O" MPD_INDEX="95" NAME="PLB_SwrDAck" SIGNAME="mb_plb_PLB_SwrDAck">
          <CONNECTIONS/>
        </PORT>
        <PORT DIR="O" MPD_INDEX="96" NAME="Bus_Error_Det" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" IS_VALID="FALSE" MPD_INDEX="0" NAME="SDCR" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="PLB_dcrAck"/>
            <PORTMAP DIR="O" PHYSICAL="PLB_dcrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="DCR_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="DCR_DBus"/>
            <PORTMAP DIR="I" PHYSICAL="DCR_Read"/>
            <PORTMAP DIR="I" PHYSICAL="DCR_Write"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1023" BASENAME="C_BASEADDR" BASEVALUE="0b1111111111" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0b0000000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x08" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDCR"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.b" INSTANCE="ilmb" IPTYPE="BUS" MHS_INDEX="2" MODCLASS="BUS" MODTYPE="lmb_v10">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_b/doc/lmb_v10.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
          <DESCRIPTION>Active High External Reset</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="sys_bus_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Bus_Struct_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGIS="RST" SIGNAME="ilmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="INSTR_ADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="ilmb_M_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IFETCH"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="ilmb_M_WriteStrobe">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="ilmb_M_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="I_AS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="Sl_DBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="Sl_Ready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="Sl_Wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="Sl_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="Sl_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_ReadStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_WriteStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_AddrStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="INSTR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_WriteDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="ilmb_LMB_Ready">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="ilmb_LMB_Wait">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IWAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="ilmb_LMB_UE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IUE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="ilmb_LMB_CE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="ICE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
      </IOINTERFACES>
    </MODULE>
    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.b" INSTANCE="dlmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_b/doc/lmb_v10.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
          <DESCRIPTION>Active High External Reset</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="sys_bus_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Bus_Struct_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGIS="RST" SIGNAME="dlmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB:ILMB]" INSTANCE="microblaze_0" PORT="RESET"/>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DATA_ADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="dlmb_M_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="READ_STROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="dlmb_M_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="WRITE_STROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="dlmb_M_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="D_AS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DATA_WRITE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="BYTE_ENABLE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="Sl_DBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="Sl_Ready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="Sl_Wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="Sl_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="Sl_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_ReadStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_WriteStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_AddrStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DATA_READ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_WriteDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="dlmb_LMB_Ready">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="dlmb_LMB_Wait">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DWAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="dlmb_LMB_UE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DUE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="dlmb_LMB_CE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DCE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
      </IOINTERFACES>
    </MODULE>
    <MODULE HWVERSION="3.00.b" INSTANCE="dlmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="virtex6"/>
        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0xa0000000">
          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
          <DESCRIPTION>Error Correction Code </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
          <DESCRIPTION>Select Interconnect </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
          <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
          <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
          <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
          <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
          <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
          <DESCRIPTION>Write Access setting </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
          <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
          <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
          <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="dlmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_ABUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_WRITEDBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_ADDRSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_READSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_WRITESTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="SL_DBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="SL_READY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="dlmb_Sl_Wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="SL_WAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="dlmb_Sl_UE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="SL_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="dlmb_Sl_CE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dlmb" PORT="SL_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGIS="RST" SIGNAME="dlmb_port_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="lmb_bram" PORT="BRAM_Rst_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="dlmb_port_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="lmb_bram" PORT="BRAM_Clk_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="dlmb_port_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="lmb_bram" PORT="BRAM_EN_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="lmb_bram" PORT="BRAM_WEN_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="lmb_bram" PORT="BRAM_Addr_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="lmb_bram" PORT="BRAM_Din_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="lmb_bram" PORT="BRAM_Dout_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SLMB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="3.00.b" INSTANCE="ilmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00001fff">
          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="virtex6"/>
        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0xa0000000">
          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
          <DESCRIPTION>Error Correction Code </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
          <DESCRIPTION>Select Interconnect </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
          <DESCRIPTION>Fault Inject Registers </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
          <DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
          <DESCRIPTION>ECC On/Off Register </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
          <DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
          <DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
          <DESCRIPTION>Write Access setting </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
          <DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
          <DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
          <DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="ilmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_ABUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_WRITEDBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_ADDRSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_READSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_WRITESTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="SL_DBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="SL_READY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="ilmb_Sl_Wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="SL_WAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="ilmb_Sl_UE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="SL_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="ilmb_Sl_CE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ilmb" PORT="SL_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGIS="RST" SIGNAME="ilmb_port_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="lmb_bram" PORT="BRAM_Rst_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="ilmb_port_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="lmb_bram" PORT="BRAM_Clk_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="lmb_bram" PORT="BRAM_EN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="lmb_bram" PORT="BRAM_WEN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="lmb_bram" PORT="BRAM_Addr_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="lmb_bram" PORT="BRAM_Din_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="lmb_bram" PORT="BRAM_Dout_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="8191" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00001fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="8192" SIZEABRV="8K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SLMB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="lmb_bram" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY" MODTYPE="bram_block">
      <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x2000">
          <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
          <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="ilmb_cntlr" PORT="BRAM_Rst_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="ilmb_port_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="ilmb_cntlr" PORT="BRAM_Clk_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="ilmb_cntlr" PORT="BRAM_EN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="ilmb_cntlr" PORT="BRAM_WEN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="ilmb_cntlr" PORT="BRAM_Addr_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="ilmb_cntlr" PORT="BRAM_Din_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="ilmb_cntlr" PORT="BRAM_Dout_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="dlmb_port_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="dlmb_cntlr" PORT="BRAM_Rst_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="dlmb_port_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="dlmb_cntlr" PORT="BRAM_Clk_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="dlmb_port_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="dlmb_cntlr" PORT="BRAM_EN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="dlmb_cntlr" PORT="BRAM_WEN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="dlmb_cntlr" PORT="BRAM_Addr_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="dlmb_cntlr" PORT="BRAM_Din_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="dlmb_cntlr" PORT="BRAM_Dout_A"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="xps_gpio_3" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80FC0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x80FCFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="7" MHS_INDEX="0" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="7" SIGNAME="fpga_0_xps_gpio_3_GPIO_IO_pin" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_gpio_3_GPIO_IO_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="7" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="7" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="7" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2163998720" BASENAME="C_BASEADDR" BASEVALUE="0x80FC0000" HIGHDECIMAL="2164064255" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FCFFFF" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="xps_gpio_4" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80FB0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x80FBFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="5">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="4" MHS_INDEX="0" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="4" SIGNAME="fpga_0_xps_gpio_4_GPIO_IO_pin" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_gpio_4_GPIO_IO_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="4" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="4" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="4" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2163933184" BASENAME="C_BASEADDR" BASEVALUE="0x80FB0000" HIGHDECIMAL="2163998719" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FBFFFF" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="xps_gpio_1" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80FE0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x80FEFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="5">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="4" MHS_INDEX="0" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="4" SIGNAME="fpga_0_xps_gpio_1_GPIO_IO_pin" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_gpio_1_GPIO_IO_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="4" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="4" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="4" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2164129792" BASENAME="C_BASEADDR" BASEVALUE="0x80FE0000" HIGHDECIMAL="2164195327" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FEFFFF" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="xps_gpio_2" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80FD0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x80FDFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="7" MHS_INDEX="0" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="7" SIGNAME="fpga_0_xps_gpio_2_GPIO_IO_pin" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_gpio_2_GPIO_IO_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="7" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="7" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" LEFT="0" LSB="7" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2164064256" BASENAME="C_BASEADDR" BASEVALUE="0x80FD0000" HIGHDECIMAL="2164129791" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FDFFFF" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="3.01.a" INSTANCE="xps_mch_emc_0" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="MEMORY_CNTLR" MODTYPE="xps_mch_emc">
      <DESCRIPTION TYPE="SHORT">XPS Multi-Channel External Memory Controller(SRAM/Flash)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Xilinx Multi-CHannel (MCH) PLBV46 external memory controller</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/doc/xps_mch_emc.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="C_NUM_BANKS_MEM" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of Memory Banks </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_NUM_CHANNELS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Number of MCH Channels </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_PRIORITY_MODE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Arbitration Mode Between PLB and MCH Interface </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_INCLUDE_PLB_IPIF" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Include PLB Slave Interface </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_INCLUDE_WRBUF" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Include Write Buffer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_MCH_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>MCH and PLB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_MCH_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of MCH</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_MCH_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="10000">
          <DESCRIPTION>MCH and PLB Clock Period </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="14" NAME="C_MEM0_BASEADDR" TYPE="std_logic_vector" VALUE="0xAE000000">
          <DESCRIPTION>Base Address of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="15" NAME="C_MEM0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xAFFFFFFF">
          <DESCRIPTION>High Address of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_MEM1_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Base Address of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="17" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="18" NAME="C_MEM2_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Base Address of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="19" NAME="C_MEM2_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="20" NAME="C_MEM3_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Base Address of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="21" NAME="C_MEM3_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_PAGEMODE_FLASH_0" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="23" NAME="C_PAGEMODE_FLASH_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_PAGEMODE_FLASH_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_PAGEMODE_FLASH_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="26" NAME="C_INCLUDE_NEGEDGE_IOREGS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Falling Edge IO Register in Interface Signals </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="27" NAME="C_MEM0_WIDTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Data Bus Width of Bank 0 </DESCRIPTION>
          <DESCRIPTION>Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="28" NAME="C_MEM1_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_MEM2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_MEM3_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="31" NAME="C_MAX_MEM_WIDTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Maximum Data Bus Width </DESCRIPTION>
          <DESCRIPTION>Maximum Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="32" NAME="C_INCLUDE_DATAWIDTH_MATCHING_0" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Execute Multiple Memory Accesses To Match Bank 0 Data Bus Width To PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="33" NAME="C_INCLUDE_DATAWIDTH_MATCHING_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 1 Data Bus Width To PLB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="34" NAME="C_INCLUDE_DATAWIDTH_MATCHING_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 2 Data Bus Width To PLB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="35" NAME="C_INCLUDE_DATAWIDTH_MATCHING_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 3 Data Bus Width To PLB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="36" NAME="C_SYNCH_MEM_0" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 0 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="37" NAME="C_SYNCH_PIPEDELAY_0" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="38" NAME="C_TCEDV_PS_MEM_0" TYPE="INTEGER" VALUE="110000">
          <DESCRIPTION>TCEDV of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="39" NAME="C_TAVDV_PS_MEM_0" TYPE="INTEGER" VALUE="110000">
          <DESCRIPTION>TAVDV of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="40" NAME="C_TPACC_PS_FLASH_0" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="41" NAME="C_THZCE_PS_MEM_0" TYPE="INTEGER" VALUE="35000">
          <DESCRIPTION>THZCE of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="42" NAME="C_THZOE_PS_MEM_0" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZOE of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="43" NAME="C_TWC_PS_MEM_0" TYPE="INTEGER" VALUE="11000">
          <DESCRIPTION>TWC of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="44" NAME="C_TWP_PS_MEM_0" TYPE="INTEGER" VALUE="70000">
          <DESCRIPTION>TWP of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="45" NAME="C_TLZWE_PS_MEM_0" TYPE="INTEGER" VALUE="35000">
          <DESCRIPTION>TLZWE of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_SYNCH_MEM_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 1 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="47" NAME="C_SYNCH_PIPEDELAY_1" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="48" NAME="C_TCEDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TCEDV of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="49" NAME="C_TAVDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TAVDV of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_TPACC_PS_FLASH_1" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="51" NAME="C_THZCE_PS_MEM_1" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZCE of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="52" NAME="C_THZOE_PS_MEM_1" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZOE of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="53" NAME="C_TWC_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TWC of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="54" NAME="C_TWP_PS_MEM_1" TYPE="INTEGER" VALUE="12000">
          <DESCRIPTION>TWP of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="55" NAME="C_TLZWE_PS_MEM_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>TLZWE of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="56" NAME="C_SYNCH_MEM_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 2 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_SYNCH_PIPEDELAY_2" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="58" NAME="C_TCEDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TCEDV of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="59" NAME="C_TAVDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TAVDV of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="60" NAME="C_TPACC_PS_FLASH_2" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="61" NAME="C_THZCE_PS_MEM_2" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZCE of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="62" NAME="C_THZOE_PS_MEM_2" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZOE of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="63" NAME="C_TWC_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TWC of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="64" NAME="C_TWP_PS_MEM_2" TYPE="INTEGER" VALUE="12000">
          <DESCRIPTION>TWP of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="65" NAME="C_TLZWE_PS_MEM_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>TLZWE of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="66" NAME="C_SYNCH_MEM_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 3 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="67" NAME="C_SYNCH_PIPEDELAY_3" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="68" NAME="C_TCEDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TCEDV of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="69" NAME="C_TAVDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TAVDV of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="70" NAME="C_TPACC_PS_FLASH_3" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="71" NAME="C_THZCE_PS_MEM_3" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZCE of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="72" NAME="C_THZOE_PS_MEM_3" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZOE of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="73" NAME="C_TWC_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TWC of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="74" NAME="C_TWP_PS_MEM_3" TYPE="INTEGER" VALUE="12000">
          <DESCRIPTION>TWP of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="75" NAME="C_TLZWE_PS_MEM_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>TLZWE of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="76" NAME="C_MCH0_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="77" NAME="C_MCH0_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="78" NAME="C_MCH0_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer Depath of Ch 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="79" NAME="C_MCH1_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="80" NAME="C_MCH1_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="81" NAME="C_MCH1_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer of Ch 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="82" NAME="C_MCH2_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="83" NAME="C_MCH2_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="84" NAME="C_MCH2_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer of Ch 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="85" NAME="C_MCH3_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="86" NAME="C_MCH3_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="87" NAME="C_MCH3_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer of Ch 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="88" NAME="C_XCL0_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="89" NAME="C_XCL0_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="90" NAME="C_XCL1_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="91" NAME="C_XCL1_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="92" NAME="C_XCL2_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="93" NAME="C_XCL2_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="94" NAME="C_XCL3_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch3</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="95" NAME="C_XCL3_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch3</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="RdClk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" IOS="emc_0" IS_INSTANTIATED="TRUE" LEFT="0" LSB="31" MHS_INDEX="1" MPD_INDEX="78" MSB="0" NAME="Mem_A" RIGHT="31" SIGNAME="0b0000000 &amp; fpga_0_xps_mch_emc_0_Mem_A_pin_vslice_7_30_concat &amp; 0b0" VECFORMULA="[0:(C_MCH_SPLB_AWIDTH-1)]">
          <SIGNALS>
            <SIGNAL NAME="0b0000000"/>
            <SIGNAL NAME="fpga_0_xps_mch_emc_0_Mem_A_pin_vslice_7_30_concat"/>
            <SIGNAL NAME="0b0"/>
          </SIGNALS>
          <DESCRIPTION>Memory Address Bus</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="0b0000000 &amp; fpga_0_xps_mch_emc_0_Mem_A_pin_vslice_7_30_concat &amp; 0b0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="80" NAME="Mem_CEN" SIGNAME="net_bsbassign0" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]">
          <DESCRIPTION>Memory Chip Enable Active Low</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_mch_emc_0_CE_inverter" PORT="Op1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="81" NAME="Mem_OEN" SIGNAME="fpga_0_xps_mch_emc_0_Mem_OEN_pin" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]">
          <DESCRIPTION>Memory Output Enable</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_mch_emc_0_Mem_OEN_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="82" NAME="Mem_WEN" SIGNAME="fpga_0_xps_mch_emc_0_Mem_WEN_pin">
          <DESCRIPTION>Memory Write Enable</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_mch_emc_0_Mem_WEN_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IOS="emc_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="15" MHS_INDEX="5" MPD_INDEX="90" MSB="0" NAME="Mem_DQ" RIGHT="15" SIGNAME="fpga_0_xps_mch_emc_0_Mem_DQ_pin" TRI_I="Mem_DQ_I" TRI_O="Mem_DQ_O" TRI_T="Mem_DQ_T" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]">
          <DESCRIPTION>Memory Data Bus</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_mch_emc_0_Mem_DQ_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="MCH_SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="2" NAME="MCH_SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="3" NAME="MCH0_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="MCH0_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="MCH0_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="6" NAME="MCH0_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="7" NAME="MCH0_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="MCH0_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="MCH0_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="10" NAME="MCH0_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="MCH1_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="MCH1_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="13" NAME="MCH1_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="MCH1_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="MCH1_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="MCH1_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="17" NAME="MCH1_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="18" NAME="MCH1_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="19" NAME="MCH2_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="20" MSB="0" NAME="MCH2_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="21" NAME="MCH2_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="MCH2_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="23" NAME="MCH2_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="24" MSB="0" NAME="MCH2_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="25" NAME="MCH2_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="MCH2_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="MCH3_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="MCH3_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="MCH3_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="30" NAME="MCH3_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="MCH3_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="MCH3_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="MCH3_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="MCH3_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="36" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="37" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="38" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="39" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="40" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="42" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="43" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="44" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="45" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="47" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="48" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="49" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="50" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="51" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="52" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="53" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="54" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="56" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="57" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="58" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="59" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="60" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="61" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="62" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="63" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="64" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="65" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="66" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="67" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="68" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="69" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="70" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="71" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="72" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="73" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="74" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="BIG" IOS="emc_0" LEFT="0" LSB="15" MPD_INDEX="75" MSB="0" NAME="Mem_DQ_I" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="emc_0" LEFT="0" LSB="15" MPD_INDEX="76" MSB="0" NAME="Mem_DQ_O" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="emc_0" LEFT="0" LSB="15" MPD_INDEX="77" MSB="0" NAME="Mem_DQ_T" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/>
        <PORT DIR="O" IOS="emc_0" MPD_INDEX="79" NAME="Mem_RPN" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Reset/Power Down</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="83" MSB="0" NAME="Mem_QWEN" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:((C_MAX_MEM_WIDTH/8)-1)]">
          <DESCRIPTION>Memory Qualified Write Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" IOS="emc_0" LEFT="0" LSB="1" MPD_INDEX="84" MSB="0" NAME="Mem_BEN" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:((C_MAX_MEM_WIDTH/8)-1)]">
          <DESCRIPTION>Memory Byte Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="emc_0" MPD_INDEX="85" NAME="Mem_CE" SIGNAME="__NOC__" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]">
          <DESCRIPTION>Memory Chip Enable Active High</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="emc_0" MPD_INDEX="86" NAME="Mem_ADV_LDN" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Advanced Burst Address/Load New Address</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="87" NAME="Mem_LBON" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Linear/Interleaved Burst Order</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="emc_0" MPD_INDEX="88" NAME="Mem_CKEN" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Clock Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="89" NAME="Mem_RNW" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Read Not Write</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCH_SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCH_SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="1" NAME="MCH0" PROTOCOL="0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCH0_Access_Control"/>
            <PORTMAP DIR="I" PHYSICAL="MCH0_Access_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH0_Access_Write"/>
            <PORTMAP DIR="O" PHYSICAL="MCH0_Access_Full"/>
            <PORTMAP DIR="O" PHYSICAL="MCH0_ReadData_Control"/>
            <PORTMAP DIR="O" PHYSICAL="MCH0_ReadData_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH0_ReadData_Read"/>
            <PORTMAP DIR="O" PHYSICAL="MCH0_ReadData_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="2" NAME="MCH1" PROTOCOL="0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCH1_Access_Control"/>
            <PORTMAP DIR="I" PHYSICAL="MCH1_Access_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH1_Access_Write"/>
            <PORTMAP DIR="O" PHYSICAL="MCH1_Access_Full"/>
            <PORTMAP DIR="O" PHYSICAL="MCH1_ReadData_Control"/>
            <PORTMAP DIR="O" PHYSICAL="MCH1_ReadData_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH1_ReadData_Read"/>
            <PORTMAP DIR="O" PHYSICAL="MCH1_ReadData_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="3" NAME="MCH2" PROTOCOL="0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCH2_Access_Control"/>
            <PORTMAP DIR="I" PHYSICAL="MCH2_Access_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH2_Access_Write"/>
            <PORTMAP DIR="O" PHYSICAL="MCH2_Access_Full"/>
            <PORTMAP DIR="O" PHYSICAL="MCH2_ReadData_Control"/>
            <PORTMAP DIR="O" PHYSICAL="MCH2_ReadData_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH2_ReadData_Read"/>
            <PORTMAP DIR="O" PHYSICAL="MCH2_ReadData_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="4" NAME="MCH3" PROTOCOL="0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCH3_Access_Control"/>
            <PORTMAP DIR="I" PHYSICAL="MCH3_Access_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH3_Access_Write"/>
            <PORTMAP DIR="O" PHYSICAL="MCH3_Access_Full"/>
            <PORTMAP DIR="O" PHYSICAL="MCH3_ReadData_Control"/>
            <PORTMAP DIR="O" PHYSICAL="MCH3_ReadData_Data"/>
            <PORTMAP DIR="I" PHYSICAL="MCH3_ReadData_Read"/>
            <PORTMAP DIR="O" PHYSICAL="MCH3_ReadData_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="emc_0" TYPE="XIL_EMC_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Mem_A"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_CEN"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_OEN"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_WEN"/>
            <PORTMAP DIR="IO" PHYSICAL="Mem_DQ"/>
            <PORTMAP DIR="I" PHYSICAL="Mem_DQ_I"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_DQ_O"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_DQ_T"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_RPN"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_BEN"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_CE"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_ADV_LDN"/>
            <PORTMAP DIR="O" PHYSICAL="Mem_CKEN"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2919235584" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0xAE000000" HIGHDECIMAL="2952790015" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0xAFFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="33554432" SIZEABRV="32M">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM1_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM1_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM2_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM2_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM3_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM3_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="4.07.a" INSTANCE="PCIe_Bridge" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="plbv46_pcie">
      <DESCRIPTION TYPE="SHORT">PLBv46 IP Interface (IPIF) to LogicCORE PCI Express Bridge</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Bridge between the PLBv46 IPIF and the Xilinx LogiCORE PCI Express Interface core</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_pcie_v4_07_a/doc/plbv46_pcie.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_SUBFAMILY" TYPE="STRING" VALUE="lx">
          <DESCRIPTION>Device Sub Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="C_IPIFBAR_NUM" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>Number of IPIF devices</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_INCLUDE_BAROFFSET_REG" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Include Registers for Each IPIF BAR High-order Bits to be Substituted in Translation.</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="C_PCIBAR_NUM" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of PCI Devices</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="5" NAME="C_NO_OF_LANES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of Lanes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="6" NAME="C_DEVICE_ID" TYPE="std_logic_vector" VALUE="0x0505">
          <DESCRIPTION>PCI Configuration Space Header Device ID</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="7" NAME="C_VENDOR_ID" TYPE="std_logic_vector" VALUE="0x10EE">
          <DESCRIPTION>PCI Configuration Space Header Vendor ID</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="8" NAME="C_CLASS_CODE" TYPE="std_logic_vector" VALUE="0x058000">
          <DESCRIPTION>PCI Configuration Space Header Class Code</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="9" NAME="C_REF_CLK_FREQ" TYPE="integer" VALUE="2">
          <DESCRIPTION>REFCLK Input Frequency</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="10" NAME="C_REV_ID" TYPE="std_logic_vector" VALUE="0x00">
          <DESCRIPTION>PCI Configuration Space Header Rev ID</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_SUBSYSTEM_ID" TYPE="std_logic_vector" VALUE="0x0000">
          <DESCRIPTION>PCI Configuration Space Header Subsystem ID</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_SUBSYSTEM_VENDOR_ID" TYPE="std_logic_vector" VALUE="0x0000">
          <DESCRIPTION>PCI Configuration Space Header Subsystem Vendor ID</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="C_COMP_TIMEOUT" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Completion Timeout</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_INCLUDE_RC" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PCIe Bridge Mode</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_MPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Master Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_MPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Master Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="17" NAME="C_MPLB_SMALLEST_SLAVE" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_MPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Bus Width of PLB Master</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="20" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="21" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="23" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x8ABF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="24" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8ABFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="26" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="27" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="28" NAME="C_IPIFBAR_0" TYPE="std_logic_vector" VALUE="0xB0000000">
          <DESCRIPTION>IPIF BAR0 Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="29" NAME="C_IPIFBAR_1" TYPE="std_logic_vector" VALUE="0xe0000000">
          <DESCRIPTION>IPIF BAR1 Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="30" NAME="C_IPIFBAR_2" TYPE="std_logic_vector" VALUE="0xc0000000">
          <DESCRIPTION>IPIF BAR2 Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="31" NAME="C_IPIFBAR_3" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>IPIF BAR3 Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="32" NAME="C_IPIFBAR_4" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>IPIF BAR4 Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="33" NAME="C_IPIFBAR_5" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>IPIF BAR5 Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="34" NAME="C_IPIFBAR_HIGHADDR_0" TYPE="std_logic_vector" VALUE="0xB0FFFFFF">
          <DESCRIPTION>IPIF BAR0 High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="35" NAME="C_IPIFBAR_HIGHADDR_1" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>IPIF BAR1 High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="36" NAME="C_IPIFBAR_HIGHADDR_2" TYPE="std_logic_vector" VALUE="0xcfffffff">
          <DESCRIPTION>IPIF BAR2 High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="37" NAME="C_IPIFBAR_HIGHADDR_3" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>IPIF BAR3 High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="38" NAME="C_IPIFBAR_HIGHADDR_4" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>IPIF BAR4 High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="39" NAME="C_IPIFBAR_HIGHADDR_5" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>IPIF BAR5 High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="40" NAME="C_IPIFBAR2PCIBAR_0" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Remote PCI device BAR to which IPIF BAR0 is translated  when configured with FIFOs
</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="41" NAME="C_IPIFBAR2PCIBAR_1" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Remote PCI device BAR to which IPIF BAR1 is translated  when configured with FIFOs
</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="42" NAME="C_IPIFBAR2PCIBAR_2" TYPE="std_logic_vector" VALUE="0xe0000000">
          <DESCRIPTION>Remote PCI device BAR to which IPIF BAR2 is translated  when configured with FIFOs
</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="43" NAME="C_IPIFBAR2PCIBAR_3" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Remote PCI device BAR to which IPIF BAR3 is translated  when configured with FIFOs
</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="44" NAME="C_IPIFBAR2PCIBAR_4" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Remote PCI device BAR to which IPIF BAR4 is translated  when configured with FIFOs
</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="45" NAME="C_IPIFBAR2PCIBAR_5" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Remote PCI device BAR to which IPIF BAR5 is translated  when configured with FIFOs
</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_IPIFBAR_AS_0" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>IPIF BAR 0 Address Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="47" NAME="C_IPIFBAR_AS_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>IPIF BAR 1 Address Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="48" NAME="C_IPIFBAR_AS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>IPIF BAR 2 Address Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="49" NAME="C_IPIFBAR_AS_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>IPIF BAR 3 Address Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_IPIFBAR_AS_4" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>IPIF BAR 4 Address Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="51" NAME="C_IPIFBAR_AS_5" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>IPIF BAR 5 Address Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="52" NAME="C_IPIFBAR_SPACE_TYPE_0" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PLBv46 Bar 0 Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="53" NAME="C_IPIFBAR_SPACE_TYPE_1" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PLBv46 Bar 1 Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="54" NAME="C_IPIFBAR_SPACE_TYPE_2" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PLBv46 Bar 2 Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="55" NAME="C_IPIFBAR_SPACE_TYPE_3" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PLBv46 Bar 3 Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="56" NAME="C_IPIFBAR_SPACE_TYPE_4" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PLBv46 Bar 4 Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_IPIFBAR_SPACE_TYPE_5" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PLBv46 Bar 5 Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="BRIDGE" MPD_INDEX="58" NAME="C_ECAM_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>ECAM Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="BRIDGE" MPD_INDEX="59" NAME="C_ECAM_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>ECAM High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="60" NAME="C_PCIBAR2IPIFBAR_0" TYPE="std_logic_vector" VALUE="0xb0000000">
          <DESCRIPTION>Remote PLB device BAR to which PCI BAR0 is translated when configured with FIFOs</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="61" NAME="C_PCIBAR2IPIFBAR_1" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Remote PLB device BAR to which PCI BAR1 is translated when configured with FIFOs</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="62" NAME="C_PCIBAR2IPIFBAR_2" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Remote PLB device BAR to which PCI BAR2 is translated when configured with FIFOs</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="63" NAME="C_PCIBAR_LEN_0" TYPE="INTEGER" VALUE="28">
          <DESCRIPTION>Power of 2 defining the Size in Bytes of PCI BAR0 Space</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="64" NAME="C_PCIBAR_LEN_1" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Power of 2 defining the Size in Bytes of PCI BAR1 Space</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="65" NAME="C_PCIBAR_LEN_2" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Power of 2 defining the Size in Bytes of PCI BAR2 Space</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="66" NAME="C_PCIBAR_AS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PCIBAR Address Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="67" NAME="C_PCIE_CAP_SLOT_IMPLEMENTED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PCIe Capabilities Register Slot Implemented</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="68" NAME="C_BOARD" TYPE="STRING" VALUE="none">
          <DESCRIPTION>Type of Board</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_DEVICE" TYPE="STRING" VALUE="6vlx240t">
          <DESCRIPTION>Device Name</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IOS="pcie_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="74" NAME="REFCLK" SIGNAME="net_bsbassign1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="PCIe_Diff_Clk" PORT="IBUF_OUT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="pcie_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="76" NAME="RXN" SIGNAME="fpga_0_PCIe_Bridge_RXN_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_PCIe_Bridge_RXN_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="pcie_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="77" NAME="RXP" SIGNAME="fpga_0_PCIe_Bridge_RXP_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_PCIe_Bridge_RXP_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="pcie_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="78" NAME="TXN" SIGNAME="fpga_0_PCIe_Bridge_TXN_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_PCIe_Bridge_TXN_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="pcie_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="79" NAME="TXP" SIGNAME="fpga_0_PCIe_Bridge_TXP_pin" VECFORMULA="[(C_NO_OF_LANES-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_PCIe_Bridge_TXP_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="80" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="PCIe_Bridge_IP2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="pcie_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="81" NAME="MSI_request" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="net_gnd">
          <CONNECTIONS>
            <CONNECTION INSTANCE="net_gnd"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="MPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_MPLB_Rst" DIR="I" MPD_INDEX="1" NAME="MPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_MPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="MPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="2" NAME="PLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MTimeout"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="3" NAME="PLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="4" NAME="PLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MAddrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="5" MSB="0" NAME="PLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="6" NAME="PLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="7" NAME="PLB_MBusy" SIGNAME="mb_plb_PLB_MBusy">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="8" NAME="PLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="9" NAME="PLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="10" NAME="PLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="11" MSB="0" NAME="PLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:(C_MPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="13" NAME="PLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="14" NAME="PLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="15" NAME="PLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="16" NAME="M_request" SIGNAME="mb_plb_M_request">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_request"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="17" MSB="0" NAME="M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_priority"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="18" NAME="M_buslock" SIGNAME="mb_plb_M_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="19" NAME="M_RNW" SIGNAME="mb_plb_M_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="20" MSB="0" NAME="M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:((C_MPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="21" MSB="0" NAME="M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="22" MSB="0" NAME="M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="23" MSB="0" NAME="M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="24" NAME="M_lockErr" SIGNAME="mb_plb_M_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_abort" DIR="O" MPD_INDEX="25" NAME="M_abort" SIGNAME="mb_plb_M_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="26" MSB="0" NAME="M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="27" MSB="0" NAME="M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:(C_MPLB_AWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="29" MSB="0" NAME="M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:(C_MPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="30" NAME="M_wrBurst" SIGNAME="mb_plb_M_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="31" NAME="M_rdBurst" SIGNAME="mb_plb_M_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="32" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="33" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="34" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="36" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="37" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="38" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="39" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="41" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="42" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="43" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="44" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="47" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="48" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="49" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="50" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="51" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="52" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="53" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="56" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="57" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="58" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="59" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="60" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="61" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="62" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="63" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="64" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="65" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="66" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="67" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="68" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="69" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="70" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="71" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="72" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="73" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="pcie_0" MPD_INDEX="75" NAME="Bridge_Clk" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="MPLB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MTimeout"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MIRQ"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MAddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MRearbitrate"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MBusy"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MWrErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MWrDAck"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MRdDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MRdWdAddr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MRdDAck"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MRdBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MWrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="M_request"/>
            <PORTMAP DIR="O" PHYSICAL="M_priority"/>
            <PORTMAP DIR="O" PHYSICAL="M_buslock"/>
            <PORTMAP DIR="O" PHYSICAL="M_RNW"/>
            <PORTMAP DIR="O" PHYSICAL="M_BE"/>
            <PORTMAP DIR="O" PHYSICAL="M_MSize"/>
            <PORTMAP DIR="O" PHYSICAL="M_size"/>
            <PORTMAP DIR="O" PHYSICAL="M_type"/>
            <PORTMAP DIR="O" PHYSICAL="M_lockErr"/>
            <PORTMAP DIR="O" PHYSICAL="M_abort"/>
            <PORTMAP DIR="O" PHYSICAL="M_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="M_UABus"/>
            <PORTMAP DIR="O" PHYSICAL="M_ABus"/>
            <PORTMAP DIR="O" PHYSICAL="M_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="M_wrBurst"/>
            <PORTMAP DIR="O" PHYSICAL="M_rdBurst"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="pcie_0" TYPE="XIL_PCIE_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="REFCLK"/>
            <PORTMAP DIR="I" PHYSICAL="RXN"/>
            <PORTMAP DIR="I" PHYSICAL="RXP"/>
            <PORTMAP DIR="O" PHYSICAL="TXN"/>
            <PORTMAP DIR="O" PHYSICAL="TXP"/>
            <PORTMAP DIR="I" PHYSICAL="MSI_request"/>
            <PORTMAP DIR="O" PHYSICAL="Bridge_Clk"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2327773184" BASENAME="C_BASEADDR" BASEVALUE="0x8ABF0000" HIGHDECIMAL="2327838719" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8ABFFFFF" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2952790016" BASENAME="C_IPIFBAR_0" BASEVALUE="0xB0000000" HIGHDECIMAL="2969567231" HIGHNAME="C_IPIFBAR_HIGHADDR_0" HIGHVALUE="0xB0FFFFFF" MEMTYPE="BRIDGE" SIZE="16777216" SIZEABRV="16M">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_IPIFBAR_1" BASEVALUE="0xe0000000" HIGHDECIMAL="4294967295" HIGHNAME="C_IPIFBAR_HIGHADDR_1" HIGHVALUE="0xffffffff" MEMTYPE="BRIDGE" SIZE="536870912" SIZEABRV="512M">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="3221225472" BASENAME="C_IPIFBAR_2" BASEVALUE="0xc0000000" HIGHDECIMAL="3489660927" HIGHNAME="C_IPIFBAR_HIGHADDR_2" HIGHVALUE="0xcfffffff" MEMTYPE="BRIDGE" SIZE="268435456" SIZEABRV="256M">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_IPIFBAR_3" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_IPIFBAR_HIGHADDR_3" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_IPIFBAR_4" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_IPIFBAR_HIGHADDR_4" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_IPIFBAR_5" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_IPIFBAR_HIGHADDR_5" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_ECAM_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_ECAM_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="BRIDGE" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="6"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="6.05.a" INSTANCE="mpmc_0" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="MEMORY_CNTLR" MODTYPE="mpmc">
      <DESCRIPTION TYPE="SHORT">Multi-Port Memory Controller(DDR/DDR2/SDRAM)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Multi-port memory controller.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v6_05_a/doc/mpmc.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="virtex6"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_SUBFAMILY" TYPE="STRING" VALUE="lx"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_DEVICE" TYPE="STRING" VALUE="6vlx240t"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_PACKAGE" TYPE="STRING" VALUE="ff1156"/>
        <PARAMETER MPD_INDEX="5" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1"/>
        <PARAMETER MPD_INDEX="6" NAME="C_SPEEDGRADE_INT" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="7" NAME="C_NUM_PORTS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>C_NUM_PORTS</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_PORT_CONFIG" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_ALL_PIMS_SHARE_ADDRESSES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Use Common Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="10" NAME="C_MPMC_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x20000000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="11" NAME="C_MPMC_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x2FFFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="12" NAME="C_MPMC_SW_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION>MPMC PIMs Software Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="13" NAME="C_MPMC_SW_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION>MPMC PIMs Software High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="14" NAME="C_SDMA_CTRL_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8ADF0000">
          <DESCRIPTION>SDMA Register Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="25" MPD_INDEX="15" NAME="C_SDMA_CTRL_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8ADFFFFF">
          <DESCRIPTION>SDMA Ctrl High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_MPMC_CTRL_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION>Control Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_MPMC_CTRL_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION>Control High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_MPMC_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="19" NAME="C_MPMC_CTRL_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="20" NAME="C_MPMC_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="21" NAME="C_MPMC_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="22" NAME="C_MPMC_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="23" NAME="C_MPMC_CTRL_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="24" NAME="C_MPMC_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="25" NAME="C_MPMC_CTRL_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="26" NAME="C_NUM_IDELAYCTRL" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of IDELAYCTRL Elements</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="27" NAME="C_IDELAYCTRL_LOC" TYPE="STRING" VALUE="NOT_SET">
          <DESCRIPTION>IDELAYCTRL Constraint Locations (Hyphen separated) </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_IODELAY_GRP" TYPE="STRING" VALUE="mpmc_0">
          <DESCRIPTION>IODELAY Grouping</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_MCB_LOC" TYPE="STRING" VALUE="NOT_SET">
          <DESCRIPTION>MCB Location</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="30" NAME="C_MMCM_EXT_LOC" TYPE="STRING" VALUE="MMCM_ADV_X0Y9">
          <DESCRIPTION>MMCM_ADV Constraint Location (external)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="31" NAME="C_MMCM_INT_LOC" TYPE="STRING" VALUE="NOT_SET">
          <DESCRIPTION>MMCM_ADV Constraint Location (internal)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="32" NAME="C_MAX_REQ_ALLOWED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of Requests MPMC can Queue per Port </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="33" NAME="C_ARB_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Turn on Arbiter Pipeline</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="34" NAME="C_WR_DATAPATH_TML_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write TML Pipeline</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="35" NAME="C_RD_DATAPATH_TML_MAX_FANOUT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Read Pipeline Max Fanout</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="36" NAME="C_ARB_USE_DEFAULT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="37" NAME="C_ARB0_ALGO" TYPE="STRING" VALUE="ROUND_ROBIN">
          <DESCRIPTION>&lt;qt&gt;&lt;b&gt;Select Arbitration Algorithm&lt;/b&gt;&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="38" NAME="C_ARB0_NUM_SLOTS" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>Number of Time Slots</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="39" NAME="C_ARB0_SLOT0" TYPE="STRING" VALUE="01234567">
          <DESCRIPTION>Time Slot 0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="40" NAME="C_ARB0_SLOT1" TYPE="STRING" VALUE="12345670">
          <DESCRIPTION>Time Slot 1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="41" NAME="C_ARB0_SLOT2" TYPE="STRING" VALUE="23456701">
          <DESCRIPTION>Time Slot 2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="42" NAME="C_ARB0_SLOT3" TYPE="STRING" VALUE="34567012">
          <DESCRIPTION>Time Slot 3</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="43" NAME="C_ARB0_SLOT4" TYPE="STRING" VALUE="45670123">
          <DESCRIPTION>Time Slot 4</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="44" NAME="C_ARB0_SLOT5" TYPE="STRING" VALUE="56701234">
          <DESCRIPTION>Time Slot 5</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="45" NAME="C_ARB0_SLOT6" TYPE="STRING" VALUE="67012345">
          <DESCRIPTION>Time Slot 6</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_ARB0_SLOT7" TYPE="STRING" VALUE="70123456">
          <DESCRIPTION>Time Slot 7</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="47" NAME="C_ARB0_SLOT8" TYPE="STRING" VALUE="01234567">
          <DESCRIPTION>Time Slot 8</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="48" NAME="C_ARB0_SLOT9" TYPE="STRING" VALUE="12345670">
          <DESCRIPTION>Time Slot 9</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="49" NAME="C_ARB0_SLOT10" TYPE="STRING" VALUE="23456701">
          <DESCRIPTION>Time Slot 10</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_ARB0_SLOT11" TYPE="STRING" VALUE="34567012">
          <DESCRIPTION>Time Slot 11</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="51" NAME="C_ARB0_SLOT12" TYPE="STRING" VALUE="45670123">
          <DESCRIPTION>Time Slot 12</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="52" NAME="C_ARB0_SLOT13" TYPE="STRING" VALUE="56701234">
          <DESCRIPTION>Time Slot 13</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="53" NAME="C_ARB0_SLOT14" TYPE="STRING" VALUE="67012345">
          <DESCRIPTION>Time Slot 14</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="54" NAME="C_ARB0_SLOT15" TYPE="STRING" VALUE="70123456">
          <DESCRIPTION>Time Slot 15</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="55" NAME="C_PM_ENABLE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Performance Monitor</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="56" NAME="C_PM_DC_WIDTH" TYPE="INTEGER" VALUE="48">
          <DESCRIPTION>&lt;qt&gt;Dead Cycle Counter Width&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_PM_GC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>&lt;qt&gt;Enable Global Cycle Counter&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="58" NAME="C_PM_GC_WIDTH" TYPE="INTEGER" VALUE="48">
          <DESCRIPTION>&lt;qt&gt;Global Cycle Counter Width&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="59" NAME="C_PM_SHIFT_CNT_BY" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>&lt;qt&gt;Shift Value of Trans Counter&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="60" NAME="C_SKIP_SIM_INIT_DELAY" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Perform Shorter Simulation Initialization</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="61" NAME="C_USE_MIG_S3_PHY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="62" NAME="C_USE_MIG_V4_PHY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="63" NAME="C_USE_MIG_V5_PHY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_USE_MIG_V6_PHY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="65" NAME="C_USE_MCB_S6_PHY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="66" NAME="C_USE_STATIC_PHY" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Static PHY</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="67" NAME="C_STATIC_PHY_RDDATA_CLK_SEL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Power-on/reset Value of RDDATA_CLK_SEL Reg </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="68" NAME="C_STATIC_PHY_RDDATA_SWAP_RISE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Power-on/reset Value of RDDATA_SWAP_RISE Reg</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="69" NAME="C_STATIC_PHY_RDEN_DELAY" TYPE="INTEGER" VALUE="5">
          <DESCRIPTION>Power-on/reset Value of RDENDELAY Reg</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="70" NAME="C_DEBUG_REG_ENABLE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Debug Registers</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="71" NAME="C_SPECIAL_BOARD" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Xilinx Special Physical Layer for Spartan3x Boards </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="72" NAME="C_USE_MIG_FLOW" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use MIG Flow</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="73" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="BANK_ROW_COLUMN"/>
        <PARAMETER MPD_INDEX="74" NAME="C_MEM_CALIBRATION_MODE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="75" NAME="C_MEM_CALIBRATION_DELAY" TYPE="STRING" VALUE="HALF"/>
        <PARAMETER MPD_INDEX="76" NAME="C_MEM_CALIBRATION_SOFT_IP" TYPE="STRING" VALUE="FALSE">
          <DESCRIPTION>Enable Soft Calibration Logic</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="77" NAME="C_MEM_CALIBRATION_BYPASS" TYPE="STRING" VALUE="NO"/>
        <PARAMETER MPD_INDEX="78" NAME="C_MPMC_MCB_DRP_CLK_PRESENT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="79" NAME="C_MEM_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Skip Input Termination Calibration</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="80" NAME="C_MEM_SKIP_DYNAMIC_CAL" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Skip Dynamic Calibration</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="81" NAME="C_MEM_SKIP_DYN_IN_TERM" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Skip Dynamic Input Termination</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="82" NAME="C_MEM_INCDEC_THRESHOLD" TYPE="INTEGER" VALUE="0x02"/>
        <PARAMETER MPD_INDEX="83" NAME="C_MEM_CHECK_MAX_INDELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="84" NAME="C_MEM_CHECK_MAX_TAP_REG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="85" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="528"/>
        <PARAMETER MPD_INDEX="86" NAME="C_MPMC_CLK_MEM_2X_PERIOD_PS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="87" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="88" NAME="C_MCB_LDQSP_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="89" NAME="C_MCB_UDQSP_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="90" NAME="C_MCB_LDQSN_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="91" NAME="C_MCB_UDQSN_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="92" NAME="C_MCB_DQ0_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="93" NAME="C_MCB_DQ1_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="94" NAME="C_MCB_DQ2_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="95" NAME="C_MCB_DQ3_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="96" NAME="C_MCB_DQ4_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="97" NAME="C_MCB_DQ5_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="98" NAME="C_MCB_DQ6_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="99" NAME="C_MCB_DQ7_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="100" NAME="C_MCB_DQ8_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="101" NAME="C_MCB_DQ9_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="102" NAME="C_MCB_DQ10_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="103" NAME="C_MCB_DQ11_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="104" NAME="C_MCB_DQ12_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="105" NAME="C_MCB_DQ13_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="106" NAME="C_MCB_DQ14_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="107" NAME="C_MCB_DQ15_TAP_DELAY_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="108" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="NOT_SET">
          <DESCRIPTION>MCB RZQ Pin Location</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="109" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="NOT_SET">
          <DESCRIPTION>MCB ZIO Pin Location</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="110" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3">
          <DESCRIPTION>Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="111" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT4JSF6464HY-1G1">
          <DESCRIPTION>Part No.</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="112" NAME="C_MEM_PART_DATA_DEPTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Data Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="113" NAME="C_MEM_PART_DATA_WIDTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="114" NAME="C_MEM_PART_NUM_BANK_BITS" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>Bank Bits</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="115" NAME="C_MEM_PART_NUM_ROW_BITS" TYPE="INTEGER" VALUE="13">
          <DESCRIPTION>Row Bits</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_MEM_PART_NUM_COL_BITS" TYPE="INTEGER" VALUE="10">
          <DESCRIPTION>Column Bits</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="117" NAME="C_MEM_PART_TRAS" TYPE="INTEGER" VALUE="37500">
          <DESCRIPTION>tRAS (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_MEM_PART_TRASMAX" TYPE="INTEGER" VALUE="70200000">
          <DESCRIPTION>tRASMAX (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="119" NAME="C_MEM_PART_TRC" TYPE="INTEGER" VALUE="50625">
          <DESCRIPTION>tRC (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="120" NAME="C_MEM_PART_TRCD" TYPE="INTEGER" VALUE="13130">
          <DESCRIPTION>tRCD (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="121" NAME="C_MEM_PART_TDQSS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="122" NAME="C_MEM_PART_TWR" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>tWR (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="123" NAME="C_MEM_PART_TRP" TYPE="INTEGER" VALUE="13130">
          <DESCRIPTION>tRP (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="124" NAME="C_MEM_PART_TMRD" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>tMRD (tCK)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="125" NAME="C_MEM_PART_TRRD" TYPE="INTEGER" VALUE="7500">
          <DESCRIPTION>tRRD (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="126" NAME="C_MEM_PART_TRFC" TYPE="INTEGER" VALUE="110000">
          <DESCRIPTION>tRFC (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="127" NAME="C_MEM_PART_TREFI" TYPE="INTEGER" VALUE="7800000">
          <DESCRIPTION>tREFI (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="128" NAME="C_MEM_PART_TAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_MEM_PART_TCCD" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>tCCD</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_MEM_PART_TWTR" TYPE="INTEGER" VALUE="7500">
          <DESCRIPTION>tWTR (ps)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="131" NAME="C_MEM_PART_TRTP" TYPE="INTEGER" VALUE="7500"/>
        <PARAMETER MPD_INDEX="132" NAME="C_MEM_PART_TZQINIT" TYPE="INTEGER" VALUE="512">
          <DESCRIPTION>tZQINIT (tCK)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="133" NAME="C_MEM_PART_TZQCS" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>tZQCS (tCK)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="134" NAME="C_MEM_PART_TPRDI" TYPE="INTEGER" VALUE="1000000"/>
        <PARAMETER MPD_INDEX="135" NAME="C_MEM_PART_TZQI" TYPE="INTEGER" VALUE="128000000"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="136" NAME="C_MEM_PART_CAS_A_FMAX" TYPE="INTEGER" VALUE="333.0">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. A Fmax&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="137" NAME="C_MEM_PART_CAS_A" TYPE="INTEGER" VALUE="5">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. A&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="138" NAME="C_MEM_PART_CAS_B_FMAX" TYPE="INTEGER" VALUE="400.0">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. B Fmax&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="139" NAME="C_MEM_PART_CAS_B" TYPE="INTEGER" VALUE="6">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. B&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="140" NAME="C_MEM_PART_CAS_C_FMAX" TYPE="INTEGER" VALUE="533.0">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. C Fmax&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="141" NAME="C_MEM_PART_CAS_C" TYPE="INTEGER" VALUE="7">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. C&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="142" NAME="C_MEM_PART_CAS_D_FMAX" TYPE="INTEGER" VALUE="1.0">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. D Fmax&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="143" NAME="C_MEM_PART_CAS_D" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>&lt;qt&gt;CAS Lat. D&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_MPMC_CLK0_PERIOD_PS" TYPE="INTEGER" VALUE="5000">
          <DESCRIPTION>&lt;qt&gt;Memory Clock Period (ps)&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="145" NAME="C_MPMC_CLK_MEM_PERIOD_PS" TYPE="INTEGER" VALUE="2500"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="147" NAME="C_MEM_ODT_TYPE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>ODT Setting</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="148" NAME="C_MEM_REDUCED_DRV" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>&lt;qt&gt;Reduced Drive Output&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="149" NAME="C_MEM_REG_DIMM" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Registered Memory</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="150" NAME="C_MEM_CLK_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Clock Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="151" NAME="C_MEM_ODT_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>ODT Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="152" NAME="C_MEM_CE_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>CE Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="153" NAME="C_MEM_CS_N_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>CSn Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="154" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13">
          <DESCRIPTION>Memory Address Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="155" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>&lt;qt&gt;Memory Bank Address Width&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="156" NAME="C_MEM_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Memory Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="157" NAME="C_MEM_BITS_DATA_PER_DQS" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="158" NAME="C_MEM_DM_WIDTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Memory DM Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="159" NAME="C_MEM_DQS_WIDTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Memory DQS Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="160" NAME="C_MEM_NUM_DIMMS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of DIMMs</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="161" NAME="C_MEM_NUM_RANKS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>No. of Ranks</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="162" NAME="C_MEM_DQS_IO_COL" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000"/>
        <PARAMETER MPD_INDEX="163" NAME="C_MEM_DQ_IO_MS" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000"/>
        <PARAMETER MPD_INDEX="164" NAME="C_DDR2_DQSN_ENABLE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable DQSN in DDR2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="165" NAME="C_INCLUDE_ECC_SUPPORT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable ECC</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="166" NAME="C_ECC_DEFAULT_ON" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>ECC Default is On</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="167" NAME="C_INCLUDE_ECC_TEST" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Include ECC Test</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="168" NAME="C_ECC_SEC_THRESHOLD" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>SEC Threshold</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="169" NAME="C_ECC_DEC_THRESHOLD" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>&lt;qt&gt;DEC Threshold&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="170" NAME="C_ECC_PEC_THRESHOLD" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>&lt;qt&gt;PEC Threshold&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="171" NAME="C_ECC_DATA_WIDTH" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="172" NAME="C_ECC_DM_WIDTH" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="173" NAME="C_ECC_DQS_WIDTH" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="174" NAME="C_MEM_PA_SR" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Partial Array Self Refresh</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="175" NAME="C_MEM_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5">
          <DESCRIPTION>CAS Write Latency</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="176" NAME="C_MEM_AUTO_SR" TYPE="STRING" VALUE="ENABLED">
          <DESCRIPTION>Auto Self Refresh</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="177" NAME="C_MEM_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL">
          <DESCRIPTION>High Temp Self Refresh</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="178" NAME="C_MEM_DYNAMIC_WRITE_ODT" TYPE="STRING" VALUE="OFF">
          <DESCRIPTION>Dynamic Write ODT Setting</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="179" NAME="C_MEM_WRLVL" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Write Leveling</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="180" NAME="C_IDELAY_CLK_FREQ" TYPE="STRING" VALUE="DEFAULT"/>
        <PARAMETER MPD_INDEX="181" NAME="C_MEM_PHASE_DETECT" TYPE="STRING" VALUE="DEFAULT"/>
        <PARAMETER MPD_INDEX="182" NAME="C_MEM_IBUF_LPWR_MODE" TYPE="STRING" VALUE="DEFAULT"/>
        <PARAMETER MPD_INDEX="183" NAME="C_MEM_IODELAY_HP_MODE" TYPE="STRING" VALUE="DEFAULT"/>
        <PARAMETER MPD_INDEX="184" NAME="C_MEM_SIM_INIT_OPTION" TYPE="STRING" VALUE="DEFAULT"/>
        <PARAMETER MPD_INDEX="185" NAME="C_MEM_SIM_CAL_OPTION" TYPE="STRING" VALUE="DEFAULT"/>
        <PARAMETER MPD_INDEX="186" NAME="C_MEM_CAL_WIDTH" TYPE="STRING" VALUE="DEFAULT"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="187" NAME="C_MEM_NDQS_COL0" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>Number of DQS groups in I/O column # 0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="188" NAME="C_MEM_NDQS_COL1" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of DQS groups in I/O column # 1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="189" NAME="C_MEM_NDQS_COL2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Number of DQS groups in I/O column # 2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="190" NAME="C_MEM_NDQS_COL3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Number of DQS groups in I/O column # 3</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="191" NAME="C_MEM_DQS_LOC_COL0" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000020100">
          <DESCRIPTION>DQS groups in column # 0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="192" NAME="C_MEM_DQS_LOC_COL1" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000003">
          <DESCRIPTION>DQS groups in column # 1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="193" NAME="C_MEM_DQS_LOC_COL2" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000">
          <DESCRIPTION>DQS groups in column # 2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="194" NAME="C_MEM_DQS_LOC_COL3" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000000000000000000000000000000000">
          <DESCRIPTION>DQS groups in column # 3</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="195" NAME="C_MAINT_PRESCALER_PERIOD" TYPE="INTEGER" VALUE="200000"/>
        <PARAMETER MPD_INDEX="196" NAME="C_TBY4TAPVALUE" TYPE="INTEGER" VALUE="9999"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="197" NAME="C_PIM0_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="198" NAME="C_PIM0_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="199" NAME="C_PIM0_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="200" NAME="C_PIM0_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="201" NAME="C_PIM0_BASETYPE" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="202" NAME="C_PIM0_SUBTYPE" TYPE="STRING" VALUE="PLB"/>
        <PARAMETER MPD_INDEX="203" NAME="C_XCL0_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="204" NAME="C_XCL0_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="205" NAME="C_XCL0_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="206" NAME="C_XCL0_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="207" NAME="C_PIM0_B_SUBTYPE" TYPE="STRING" VALUE="PLB"/>
        <PARAMETER MPD_INDEX="208" NAME="C_XCL0_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="209" NAME="C_XCL0_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="210" NAME="C_SPLB0_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="211" NAME="C_SPLB0_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="212" NAME="C_SPLB0_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="213" NAME="C_SPLB0_NUM_MASTERS" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="214" NAME="C_SPLB0_MID_WIDTH" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="215" NAME="C_SPLB0_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="216" NAME="C_SPLB0_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="217" NAME="C_SPLB0_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="218" NAME="C_SDMA_CTRL0_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="219" NAME="C_SDMA_CTRL0_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="220" NAME="C_SDMA_CTRL0_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="221" NAME="C_SDMA_CTRL0_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="222" NAME="C_SDMA_CTRL0_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="223" NAME="C_SDMA_CTRL0_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="224" NAME="C_SDMA_CTRL0_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="225" NAME="C_SDMA_CTRL0_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="226" NAME="C_SDMA_CTRL0_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="227" NAME="C_SDMA_CTRL0_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="228" NAME="C_SDMA0_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable TX Completed Err</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="229" NAME="C_SDMA0_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="230" NAME="C_SDMA0_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="231" NAME="C_SDMA0_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="232" NAME="C_PPC440MC0_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="233" NAME="C_PPC440MC0_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="234" NAME="C_VFBC0_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="235" NAME="C_VFBC0_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="236" NAME="C_VFBC0_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="237" NAME="C_VFBC0_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="238" NAME="C_VFBC0_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="239" NAME="C_PI0_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="240" NAME="C_PI0_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="241" NAME="C_PI0_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="242" NAME="C_PI0_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="243" NAME="C_PI0_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="244" NAME="C_PI0_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="245" NAME="C_PI0_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="246" NAME="C_PI0_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="247" NAME="C_PI0_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="248" NAME="C_PIM1_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="249" NAME="C_PIM1_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="250" NAME="C_PIM1_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="251" NAME="C_PIM1_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="252" NAME="C_PIM1_BASETYPE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="253" NAME="C_PIM1_SUBTYPE" TYPE="STRING" VALUE="IXCL"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="254" NAME="C_XCL1_LINESIZE" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="255" NAME="C_XCL1_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="256" NAME="C_XCL1_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="257" NAME="C_XCL1_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="258" NAME="C_PIM1_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="259" NAME="C_XCL1_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="260" NAME="C_XCL1_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="261" NAME="C_SPLB1_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="262" NAME="C_SPLB1_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="263" NAME="C_SPLB1_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="264" NAME="C_SPLB1_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="265" NAME="C_SPLB1_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="266" NAME="C_SPLB1_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="267" NAME="C_SPLB1_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="268" NAME="C_SPLB1_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="269" NAME="C_SDMA_CTRL1_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="270" NAME="C_SDMA_CTRL1_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="271" NAME="C_SDMA_CTRL1_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="272" NAME="C_SDMA_CTRL1_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="273" NAME="C_SDMA_CTRL1_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="274" NAME="C_SDMA_CTRL1_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="275" NAME="C_SDMA_CTRL1_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="276" NAME="C_SDMA_CTRL1_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="277" NAME="C_SDMA_CTRL1_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="278" NAME="C_SDMA_CTRL1_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="279" NAME="C_SDMA1_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on TX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="280" NAME="C_SDMA1_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="281" NAME="C_SDMA1_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="282" NAME="C_SDMA1_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="283" NAME="C_PPC440MC1_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="284" NAME="C_PPC440MC1_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="285" NAME="C_VFBC1_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="286" NAME="C_VFBC1_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="287" NAME="C_VFBC1_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="288" NAME="C_VFBC1_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="289" NAME="C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="290" NAME="C_PI1_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="291" NAME="C_PI1_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="292" NAME="C_PI1_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="293" NAME="C_PI1_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="294" NAME="C_PI1_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="295" NAME="C_PI1_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="296" NAME="C_PI1_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="297" NAME="C_PI1_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="298" NAME="C_PI1_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="299" NAME="C_PIM2_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="300" NAME="C_PIM2_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="301" NAME="C_PIM2_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="302" NAME="C_PIM2_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="303" NAME="C_PIM2_BASETYPE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="304" NAME="C_PIM2_SUBTYPE" TYPE="STRING" VALUE="DXCL"/>
        <PARAMETER MPD_INDEX="305" NAME="C_XCL2_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="306" NAME="C_XCL2_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="307" NAME="C_XCL2_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="308" NAME="C_XCL2_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="309" NAME="C_PIM2_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="310" NAME="C_XCL2_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="311" NAME="C_XCL2_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="312" NAME="C_SPLB2_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="313" NAME="C_SPLB2_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="314" NAME="C_SPLB2_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="315" NAME="C_SPLB2_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="316" NAME="C_SPLB2_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="317" NAME="C_SPLB2_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="318" NAME="C_SPLB2_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="319" NAME="C_SPLB2_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="320" NAME="C_SDMA_CTRL2_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="321" NAME="C_SDMA_CTRL2_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="322" NAME="C_SDMA_CTRL2_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="323" NAME="C_SDMA_CTRL2_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="324" NAME="C_SDMA_CTRL2_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="325" NAME="C_SDMA_CTRL2_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="326" NAME="C_SDMA_CTRL2_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="327" NAME="C_SDMA_CTRL2_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="328" NAME="C_SDMA_CTRL2_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="329" NAME="C_SDMA_CTRL2_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="330" NAME="C_SDMA2_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on TX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="331" NAME="C_SDMA2_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="332" NAME="C_SDMA2_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="333" NAME="C_SDMA2_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="334" NAME="C_PPC440MC2_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="335" NAME="C_PPC440MC2_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="336" NAME="C_VFBC2_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="337" NAME="C_VFBC2_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="338" NAME="C_VFBC2_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="339" NAME="C_VFBC2_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="340" NAME="C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="341" NAME="C_PI2_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="342" NAME="C_PI2_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="343" NAME="C_PI2_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="344" NAME="C_PI2_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="345" NAME="C_PI2_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="346" NAME="C_PI2_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="347" NAME="C_PI2_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="348" NAME="C_PI2_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="349" NAME="C_PI2_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="350" NAME="C_PIM3_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="351" NAME="C_PIM3_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="352" NAME="C_PIM3_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="353" NAME="C_PIM3_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="354" NAME="C_PIM3_BASETYPE" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="355" NAME="C_PIM3_SUBTYPE" TYPE="STRING" VALUE="SDMA"/>
        <PARAMETER MPD_INDEX="356" NAME="C_XCL3_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="357" NAME="C_XCL3_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="358" NAME="C_XCL3_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="359" NAME="C_XCL3_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="360" NAME="C_PIM3_B_SUBTYPE" TYPE="STRING" VALUE="SDMA"/>
        <PARAMETER MPD_INDEX="361" NAME="C_XCL3_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="362" NAME="C_XCL3_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="363" NAME="C_SPLB3_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="364" NAME="C_SPLB3_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="365" NAME="C_SPLB3_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="366" NAME="C_SPLB3_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="367" NAME="C_SPLB3_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="368" NAME="C_SPLB3_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="369" NAME="C_SPLB3_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="370" NAME="C_SPLB3_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="371" NAME="C_SDMA_CTRL3_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="372" NAME="C_SDMA_CTRL3_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="373" NAME="C_SDMA_CTRL3_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="374" NAME="C_SDMA_CTRL3_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="375" NAME="C_SDMA_CTRL3_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="376" NAME="C_SDMA_CTRL3_NUM_MASTERS" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="377" NAME="C_SDMA_CTRL3_MID_WIDTH" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="378" NAME="C_SDMA_CTRL3_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="379" NAME="C_SDMA_CTRL3_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="380" NAME="C_SDMA_CTRL3_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="381" NAME="C_SDMA3_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on TX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="382" NAME="C_SDMA3_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="383" NAME="C_SDMA3_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="384" NAME="C_SDMA3_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="385" NAME="C_PPC440MC3_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="386" NAME="C_PPC440MC3_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="387" NAME="C_VFBC3_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="388" NAME="C_VFBC3_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="389" NAME="C_VFBC3_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="390" NAME="C_VFBC3_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="391" NAME="C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="392" NAME="C_PI3_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="393" NAME="C_PI3_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="394" NAME="C_PI3_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="395" NAME="C_PI3_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="396" NAME="C_PI3_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="397" NAME="C_PI3_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="398" NAME="C_PI3_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="399" NAME="C_PI3_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="400" NAME="C_PI3_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="401" NAME="C_PIM4_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="402" NAME="C_PIM4_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="403" NAME="C_PIM4_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="404" NAME="C_PIM4_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="405" NAME="C_PIM4_BASETYPE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="406" NAME="C_PIM4_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="407" NAME="C_XCL4_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="408" NAME="C_XCL4_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="409" NAME="C_XCL4_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="410" NAME="C_XCL4_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="411" NAME="C_PIM4_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="412" NAME="C_XCL4_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="413" NAME="C_XCL4_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="414" NAME="C_SPLB4_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="415" NAME="C_SPLB4_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="416" NAME="C_SPLB4_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="417" NAME="C_SPLB4_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="418" NAME="C_SPLB4_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="419" NAME="C_SPLB4_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="420" NAME="C_SPLB4_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="421" NAME="C_SPLB4_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="422" NAME="C_SDMA_CTRL4_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="423" NAME="C_SDMA_CTRL4_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="424" NAME="C_SDMA_CTRL4_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="425" NAME="C_SDMA_CTRL4_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="426" NAME="C_SDMA_CTRL4_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="427" NAME="C_SDMA_CTRL4_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="428" NAME="C_SDMA_CTRL4_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="429" NAME="C_SDMA_CTRL4_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="430" NAME="C_SDMA_CTRL4_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="431" NAME="C_SDMA_CTRL4_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="432" NAME="C_SDMA4_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on TX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="433" NAME="C_SDMA4_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="434" NAME="C_SDMA4_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="435" NAME="C_SDMA4_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="436" NAME="C_PPC440MC4_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="437" NAME="C_PPC440MC4_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="438" NAME="C_VFBC4_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="439" NAME="C_VFBC4_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="440" NAME="C_VFBC4_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="441" NAME="C_VFBC4_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="442" NAME="C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="443" NAME="C_PI4_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="444" NAME="C_PI4_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="445" NAME="C_PI4_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="446" NAME="C_PI4_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="447" NAME="C_PI4_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="448" NAME="C_PI4_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="449" NAME="C_PI4_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="450" NAME="C_PI4_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="451" NAME="C_PI4_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="452" NAME="C_PIM5_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="453" NAME="C_PIM5_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="454" NAME="C_PIM5_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="455" NAME="C_PIM5_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="456" NAME="C_PIM5_BASETYPE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="457" NAME="C_PIM5_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="458" NAME="C_XCL5_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="459" NAME="C_XCL5_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="460" NAME="C_XCL5_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="461" NAME="C_XCL5_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="462" NAME="C_PIM5_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="463" NAME="C_XCL5_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="464" NAME="C_XCL5_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="465" NAME="C_SPLB5_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="466" NAME="C_SPLB5_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="467" NAME="C_SPLB5_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="468" NAME="C_SPLB5_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="469" NAME="C_SPLB5_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="470" NAME="C_SPLB5_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="471" NAME="C_SPLB5_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="472" NAME="C_SPLB5_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="473" NAME="C_SDMA_CTRL5_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="474" NAME="C_SDMA_CTRL5_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="475" NAME="C_SDMA_CTRL5_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="476" NAME="C_SDMA_CTRL5_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="477" NAME="C_SDMA_CTRL5_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="478" NAME="C_SDMA_CTRL5_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="479" NAME="C_SDMA_CTRL5_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="480" NAME="C_SDMA_CTRL5_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="481" NAME="C_SDMA_CTRL5_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="482" NAME="C_SDMA_CTRL5_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="483" NAME="C_SDMA5_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on TX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="484" NAME="C_SDMA5_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="485" NAME="C_SDMA5_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="486" NAME="C_SDMA5_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="487" NAME="C_PPC440MC5_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="488" NAME="C_PPC440MC5_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="489" NAME="C_VFBC5_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="490" NAME="C_VFBC5_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="491" NAME="C_VFBC5_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="492" NAME="C_VFBC5_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="493" NAME="C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="494" NAME="C_PI5_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="495" NAME="C_PI5_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="496" NAME="C_PI5_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="497" NAME="C_PI5_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="498" NAME="C_PI5_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="499" NAME="C_PI5_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="500" NAME="C_PI5_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="501" NAME="C_PI5_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="502" NAME="C_PI5_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="503" NAME="C_PIM6_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="504" NAME="C_PIM6_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="505" NAME="C_PIM6_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="506" NAME="C_PIM6_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="507" NAME="C_PIM6_BASETYPE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="508" NAME="C_PIM6_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="509" NAME="C_XCL6_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="510" NAME="C_XCL6_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="511" NAME="C_XCL6_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="512" NAME="C_XCL6_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="513" NAME="C_PIM6_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="514" NAME="C_XCL6_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="515" NAME="C_XCL6_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="516" NAME="C_SPLB6_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="517" NAME="C_SPLB6_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="518" NAME="C_SPLB6_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="519" NAME="C_SPLB6_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="520" NAME="C_SPLB6_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="521" NAME="C_SPLB6_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="522" NAME="C_SPLB6_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="523" NAME="C_SPLB6_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="524" NAME="C_SDMA_CTRL6_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="525" NAME="C_SDMA_CTRL6_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="526" NAME="C_SDMA_CTRL6_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="527" NAME="C_SDMA_CTRL6_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="528" NAME="C_SDMA_CTRL6_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="529" NAME="C_SDMA_CTRL6_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="530" NAME="C_SDMA_CTRL6_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="531" NAME="C_SDMA_CTRL6_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="532" NAME="C_SDMA_CTRL6_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="533" NAME="C_SDMA_CTRL6_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="534" NAME="C_SDMA6_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on TX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="535" NAME="C_SDMA6_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="536" NAME="C_SDMA6_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="537" NAME="C_SDMA6_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="538" NAME="C_PPC440MC6_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="539" NAME="C_PPC440MC6_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="540" NAME="C_VFBC6_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="541" NAME="C_VFBC6_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="542" NAME="C_VFBC6_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="543" NAME="C_VFBC6_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="544" NAME="C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="545" NAME="C_PI6_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="546" NAME="C_PI6_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="547" NAME="C_PI6_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="548" NAME="C_PI6_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="549" NAME="C_PI6_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="550" NAME="C_PI6_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="551" NAME="C_PI6_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="552" NAME="C_PI6_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="553" NAME="C_PI6_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="554" NAME="C_PIM7_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="555" NAME="C_PIM7_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="556" NAME="C_PIM7_OFFSET" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="557" NAME="C_PIM7_DATA_WIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>NPI Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="558" NAME="C_PIM7_BASETYPE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="559" NAME="C_PIM7_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="560" NAME="C_XCL7_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cache Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="561" NAME="C_XCL7_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="562" NAME="C_XCL7_PIPE_STAGES" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>XCL Pipe Stage </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="563" NAME="C_XCL7_B_IN_USE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Channel B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="564" NAME="C_PIM7_B_SUBTYPE" TYPE="STRING" VALUE="INACTIVE"/>
        <PARAMETER MPD_INDEX="565" NAME="C_XCL7_B_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Channel B Line Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="566" NAME="C_XCL7_B_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel B Write Transfer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="567" NAME="C_SPLB7_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="568" NAME="C_SPLB7_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="569" NAME="C_SPLB7_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Native Data Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="570" NAME="C_SPLB7_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="571" NAME="C_SPLB7_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="572" NAME="C_SPLB7_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="573" NAME="C_SPLB7_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="574" NAME="C_SPLB7_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="575" NAME="C_SDMA_CTRL7_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="576" NAME="C_SDMA_CTRL7_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="577" NAME="C_SDMA_CTRL7_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="578" NAME="C_SDMA_CTRL7_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER MPD_INDEX="579" NAME="C_SDMA_CTRL7_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="580" NAME="C_SDMA_CTRL7_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="581" NAME="C_SDMA_CTRL7_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="582" NAME="C_SDMA_CTRL7_P2P" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="583" NAME="C_SDMA_CTRL7_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="584" NAME="C_SDMA_CTRL7_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="585" NAME="C_SDMA7_COMPLETED_ERR_TX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on TX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="586" NAME="C_SDMA7_COMPLETED_ERR_RX" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable Completed Err on RX</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="587" NAME="C_SDMA7_PRESCALAR" TYPE="INTEGER" VALUE="1023">
          <DESCRIPTION>Clock Div. of Int. Timer Clk</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="588" NAME="C_SDMA7_PI2LL_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>MPMC to SDMA Clk Ratio</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="589" NAME="C_PPC440MC7_BURST_LENGTH" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Burst Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="590" NAME="C_PPC440MC7_PIPE_STAGES" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Pipe Stage</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="591" NAME="C_VFBC7_CMD_FIFO_DEPTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Command FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="592" NAME="C_VFBC7_CMD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Command FIFO Almost Full Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="593" NAME="C_VFBC7_RDWD_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>VFBC Data FIFO Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="594" NAME="C_VFBC7_RDWD_FIFO_DEPTH" TYPE="INTEGER" VALUE="1024">
          <DESCRIPTION>VFBC Data FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="595" NAME="C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>VFBC Data FIFO Almost Full/Empty Count</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="596" NAME="C_PI7_RD_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="597" NAME="C_PI7_WR_FIFO_TYPE" TYPE="STRING" VALUE="BRAM"/>
        <PARAMETER MPD_INDEX="598" NAME="C_PI7_ADDRACK_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="599" NAME="C_PI7_RD_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="600" NAME="C_PI7_RD_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="601" NAME="C_PI7_WR_FIFO_APP_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="602" NAME="C_PI7_WR_FIFO_MEM_PIPELINE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="603" NAME="C_PI7_PM_USED" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="604" NAME="C_PI7_PM_DC_CNTR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION></DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="605" NAME="C_WR_TRAINING_PORT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Specifies Which Port's Write FIFO will be used for Memory Initialization </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="606" NAME="C_ARB_BRAM_INIT_00" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000"/>
        <PARAMETER MPD_INDEX="607" NAME="C_ARB_BRAM_INIT_01" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/>
        <PARAMETER MPD_INDEX="608" NAME="C_ARB_BRAM_INIT_02" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000"/>
        <PARAMETER MPD_INDEX="609" NAME="C_ARB_BRAM_INIT_03" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/>
        <PARAMETER MPD_INDEX="610" NAME="C_ARB_BRAM_INIT_04" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000"/>
        <PARAMETER MPD_INDEX="611" NAME="C_ARB_BRAM_INIT_05" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/>
        <PARAMETER MPD_INDEX="612" NAME="C_ARB_BRAM_INIT_06" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000"/>
        <PARAMETER MPD_INDEX="613" NAME="C_ARB_BRAM_INIT_07" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="614" NAME="C_NCK_PER_CLK" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="615" NAME="C_TWR" TYPE="INTEGER" VALUE="15000"/>
        <PARAMETER MPD_INDEX="616" NAME="C_CTRL_COMPLETE_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="617" NAME="C_CTRL_IS_WRITE_INDEX" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="618" NAME="C_CTRL_PHYIF_RAS_N_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="619" NAME="C_CTRL_PHYIF_CAS_N_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="620" NAME="C_CTRL_PHYIF_WE_N_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="621" NAME="C_CTRL_RMW_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="622" NAME="C_CTRL_SKIP_0_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="623" NAME="C_CTRL_PHYIF_DQS_O_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="624" NAME="C_CTRL_SKIP_1_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="625" NAME="C_CTRL_DP_RDFIFO_PUSH_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="626" NAME="C_CTRL_SKIP_2_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="627" NAME="C_CTRL_AP_COL_CNT_LOAD_INDEX" TYPE="INTEGER" VALUE="12"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="628" NAME="C_CTRL_AP_COL_CNT_ENABLE_INDEX" TYPE="INTEGER" VALUE="13"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="629" NAME="C_CTRL_AP_PRECHARGE_ADDR10_INDEX" TYPE="INTEGER" VALUE="14"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="630" NAME="C_CTRL_AP_ROW_COL_SEL_INDEX" TYPE="INTEGER" VALUE="15"/>
        <PARAMETER MPD_INDEX="631" NAME="C_CTRL_PHYIF_FORCE_DM_INDEX" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="632" NAME="C_CTRL_REPEAT4_INDEX" TYPE="INTEGER" VALUE="17"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="633" NAME="C_CTRL_DFI_RAS_N_0_INDEX" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="634" NAME="C_CTRL_DFI_CAS_N_0_INDEX" TYPE="INTEGER" VALUE="3"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="635" NAME="C_CTRL_DFI_WE_N_0_INDEX" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="636" NAME="C_CTRL_DFI_RAS_N_1_INDEX" TYPE="INTEGER" VALUE="20"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="637" NAME="C_CTRL_DFI_CAS_N_1_INDEX" TYPE="INTEGER" VALUE="21"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="638" NAME="C_CTRL_DFI_WE_N_1_INDEX" TYPE="INTEGER" VALUE="22"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="639" NAME="C_CTRL_DP_WRFIFO_POP_INDEX" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="640" NAME="C_CTRL_DFI_WRDATA_EN_INDEX" TYPE="INTEGER" VALUE="18"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="641" NAME="C_CTRL_DFI_RDDATA_EN_INDEX" TYPE="INTEGER" VALUE="19"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="642" NAME="C_CTRL_AP_OTF_ADDR12_INDEX" TYPE="INTEGER" VALUE="23"/>
        <PARAMETER MPD_INDEX="643" NAME="C_CTRL_ARB_RDMODWR_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="644" NAME="C_CTRL_AP_COL_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="645" NAME="C_CTRL_AP_PI_ADDR_CE_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="646" NAME="C_CTRL_AP_PORT_SELECT_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="647" NAME="C_CTRL_AP_PIPELINE1_CE_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="648" NAME="C_CTRL_DP_LOAD_RDWDADDR_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="649" NAME="C_CTRL_DP_RDFIFO_WHICHPORT_DELAY" TYPE="INTEGER" VALUE="15"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="650" NAME="C_CTRL_DP_SIZE_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="651" NAME="C_CTRL_DP_WRFIFO_WHICHPORT_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="652" NAME="C_CTRL_PHYIF_DUMMYREADSTART_DELAY" TYPE="INTEGER" VALUE="5"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="653" NAME="C_CTRL_Q0_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="654" NAME="C_CTRL_Q1_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="655" NAME="C_CTRL_Q2_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="656" NAME="C_CTRL_Q3_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="657" NAME="C_CTRL_Q4_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER MPD_INDEX="658" NAME="C_CTRL_Q5_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="659" NAME="C_CTRL_Q6_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="660" NAME="C_CTRL_Q7_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="661" NAME="C_CTRL_Q8_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="662" NAME="C_CTRL_Q9_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="663" NAME="C_CTRL_Q10_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="664" NAME="C_CTRL_Q11_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="665" NAME="C_CTRL_Q12_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="666" NAME="C_CTRL_Q13_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="667" NAME="C_CTRL_Q14_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="668" NAME="C_CTRL_Q15_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="669" NAME="C_CTRL_Q16_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="670" NAME="C_CTRL_Q17_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="671" NAME="C_CTRL_Q18_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="672" NAME="C_CTRL_Q19_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="673" NAME="C_CTRL_Q20_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="674" NAME="C_CTRL_Q21_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="675" NAME="C_CTRL_Q22_DELAY" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="676" NAME="C_CTRL_Q23_DELAY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="677" NAME="C_CTRL_Q24_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="678" NAME="C_CTRL_Q25_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="679" NAME="C_CTRL_Q26_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="680" NAME="C_CTRL_Q27_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="681" NAME="C_CTRL_Q28_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="682" NAME="C_CTRL_Q29_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="683" NAME="C_CTRL_Q30_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="684" NAME="C_CTRL_Q31_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="685" NAME="C_CTRL_Q32_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="686" NAME="C_CTRL_Q33_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="687" NAME="C_CTRL_Q34_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="688" NAME="C_CTRL_Q35_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="689" NAME="C_SKIP_1_VALUE" TYPE="INTEGER" VALUE="0x001"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="690" NAME="C_SKIP_2_VALUE" TYPE="INTEGER" VALUE="0x001"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="691" NAME="C_SKIP_3_VALUE" TYPE="INTEGER" VALUE="0x001"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="692" NAME="C_SKIP_4_VALUE" TYPE="INTEGER" VALUE="0x001"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="693" NAME="C_SKIP_5_VALUE" TYPE="INTEGER" VALUE="0x001"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="694" NAME="C_SKIP_6_VALUE" TYPE="INTEGER" VALUE="0x001"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="695" NAME="C_SKIP_7_VALUE" TYPE="INTEGER" VALUE="0x001"/>
        <PARAMETER MPD_INDEX="696" NAME="C_B16_REPEAT_CNT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="697" NAME="C_B32_REPEAT_CNT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="698" NAME="C_B64_REPEAT_CNT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="699" NAME="C_ZQCS_REPEAT_CNT" TYPE="INTEGER" VALUE="6"/>
        <PARAMETER MPD_INDEX="700" NAME="C_BASEADDR_CTRL0" TYPE="STD_LOGIC_VECTOR" VALUE="0x000"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="701" NAME="C_HIGHADDR_CTRL0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00f"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="702" NAME="C_BASEADDR_CTRL1" TYPE="STD_LOGIC_VECTOR" VALUE="0x010"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="703" NAME="C_HIGHADDR_CTRL1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01b"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="704" NAME="C_BASEADDR_CTRL2" TYPE="STD_LOGIC_VECTOR" VALUE="0x01c"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="705" NAME="C_HIGHADDR_CTRL2" TYPE="STD_LOGIC_VECTOR" VALUE="0x02b"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="706" NAME="C_BASEADDR_CTRL3" TYPE="STD_LOGIC_VECTOR" VALUE="0x02c"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="707" NAME="C_HIGHADDR_CTRL3" TYPE="STD_LOGIC_VECTOR" VALUE="0x037"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="708" NAME="C_BASEADDR_CTRL4" TYPE="STD_LOGIC_VECTOR" VALUE="0x038"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="709" NAME="C_HIGHADDR_CTRL4" TYPE="STD_LOGIC_VECTOR" VALUE="0x047"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="710" NAME="C_BASEADDR_CTRL5" TYPE="STD_LOGIC_VECTOR" VALUE="0x048"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="711" NAME="C_HIGHADDR_CTRL5" TYPE="STD_LOGIC_VECTOR" VALUE="0x053"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="712" NAME="C_BASEADDR_CTRL6" TYPE="STD_LOGIC_VECTOR" VALUE="0x054"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="713" NAME="C_HIGHADDR_CTRL6" TYPE="STD_LOGIC_VECTOR" VALUE="0x063"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="714" NAME="C_BASEADDR_CTRL7" TYPE="STD_LOGIC_VECTOR" VALUE="0x064"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="715" NAME="C_HIGHADDR_CTRL7" TYPE="STD_LOGIC_VECTOR" VALUE="0x06f"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="716" NAME="C_BASEADDR_CTRL8" TYPE="STD_LOGIC_VECTOR" VALUE="0x070"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="717" NAME="C_HIGHADDR_CTRL8" TYPE="STD_LOGIC_VECTOR" VALUE="0x081"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="718" NAME="C_BASEADDR_CTRL9" TYPE="STD_LOGIC_VECTOR" VALUE="0x082"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="719" NAME="C_HIGHADDR_CTRL9" TYPE="STD_LOGIC_VECTOR" VALUE="0x08e"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="720" NAME="C_BASEADDR_CTRL10" TYPE="STD_LOGIC_VECTOR" VALUE="0x08f"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="721" NAME="C_HIGHADDR_CTRL10" TYPE="STD_LOGIC_VECTOR" VALUE="0x0a4"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="722" NAME="C_BASEADDR_CTRL11" TYPE="STD_LOGIC_VECTOR" VALUE="0x0a5"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="723" NAME="C_HIGHADDR_CTRL11" TYPE="STD_LOGIC_VECTOR" VALUE="0x0b5"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="724" NAME="C_BASEADDR_CTRL12" TYPE="STD_LOGIC_VECTOR" VALUE="0x0b6"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="725" NAME="C_HIGHADDR_CTRL12" TYPE="STD_LOGIC_VECTOR" VALUE="0x0d3"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="726" NAME="C_BASEADDR_CTRL13" TYPE="STD_LOGIC_VECTOR" VALUE="0x0d4"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="727" NAME="C_HIGHADDR_CTRL13" TYPE="STD_LOGIC_VECTOR" VALUE="0x0ec"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="728" NAME="C_BASEADDR_CTRL14" TYPE="STD_LOGIC_VECTOR" VALUE="0x0ed"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="729" NAME="C_HIGHADDR_CTRL14" TYPE="STD_LOGIC_VECTOR" VALUE="0x106"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="730" NAME="C_BASEADDR_CTRL15" TYPE="STD_LOGIC_VECTOR" VALUE="0x107"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="731" NAME="C_HIGHADDR_CTRL15" TYPE="STD_LOGIC_VECTOR" VALUE="0x107"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="732" NAME="C_BASEADDR_CTRL16" TYPE="STD_LOGIC_VECTOR" VALUE="0x108"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="733" NAME="C_HIGHADDR_CTRL16" TYPE="STD_LOGIC_VECTOR" VALUE="0x110"/>
        <PARAMETER MPD_INDEX="734" NAME="C_CTRL_BRAM_INIT_3F" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="735" NAME="C_CTRL_BRAM_INIT_3E" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="736" NAME="C_CTRL_BRAM_INIT_3D" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="737" NAME="C_CTRL_BRAM_INIT_3C" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="738" NAME="C_CTRL_BRAM_INIT_3B" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="739" NAME="C_CTRL_BRAM_INIT_3A" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="740" NAME="C_CTRL_BRAM_INIT_39" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="741" NAME="C_CTRL_BRAM_INIT_38" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="742" NAME="C_CTRL_BRAM_INIT_37" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="743" NAME="C_CTRL_BRAM_INIT_36" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="744" NAME="C_CTRL_BRAM_INIT_35" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="745" NAME="C_CTRL_BRAM_INIT_34" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="746" NAME="C_CTRL_BRAM_INIT_33" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="747" NAME="C_CTRL_BRAM_INIT_32" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="748" NAME="C_CTRL_BRAM_INIT_31" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="749" NAME="C_CTRL_BRAM_INIT_30" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="750" NAME="C_CTRL_BRAM_INIT_2F" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="751" NAME="C_CTRL_BRAM_INIT_2E" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="752" NAME="C_CTRL_BRAM_INIT_2D" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="753" NAME="C_CTRL_BRAM_INIT_2C" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="754" NAME="C_CTRL_BRAM_INIT_2B" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="755" NAME="C_CTRL_BRAM_INIT_2A" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="756" NAME="C_CTRL_BRAM_INIT_29" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="757" NAME="C_CTRL_BRAM_INIT_28" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="758" NAME="C_CTRL_BRAM_INIT_27" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="759" NAME="C_CTRL_BRAM_INIT_26" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="760" NAME="C_CTRL_BRAM_INIT_25" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="761" NAME="C_CTRL_BRAM_INIT_24" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER MPD_INDEX="762" NAME="C_CTRL_BRAM_INIT_23" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="763" NAME="C_CTRL_BRAM_INIT_22" TYPE="STD_LOGIC_VECTOR" VALUE="0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC0070001C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="764" NAME="C_CTRL_BRAM_INIT_21" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001D0070001C0072001C0070000C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="765" NAME="C_CTRL_BRAM_INIT_20" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001C0070001C0070001D0070001C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="766" NAME="C_CTRL_BRAM_INIT_1F" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001C0070001C0070001C0070001C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="767" NAME="C_CTRL_BRAM_INIT_1E" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0070001C0070001C0070001C0070001C0040001C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="768" NAME="C_CTRL_BRAM_INIT_1D" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C007040080070001C0070001C0070001C0070001C0020401C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="769" NAME="C_CTRL_BRAM_INIT_1C" TYPE="STD_LOGIC_VECTOR" VALUE="0x0078001D00D8201C0078001C00D8201C0078001C00D8201C0078001C00D8201C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="770" NAME="C_CTRL_BRAM_INIT_1B" TYPE="STD_LOGIC_VECTOR" VALUE="0x0078001C00D8201C0078001C00D8201C0078001C00D8201C0078001C00D8201C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="771" NAME="C_CTRL_BRAM_INIT_1A" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101C0070001C007080180070001C0070001E0070001E0070001E0070400A"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="772" NAME="C_CTRL_BRAM_INIT_19" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001F0070001E0070001E0070001E0070201E0074001E0094201E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="773" NAME="C_CTRL_BRAM_INIT_18" TYPE="STD_LOGIC_VECTOR" VALUE="0x0074011E0094211E0074011E0094211E0074011E0094211E0074011E0094211E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="774" NAME="C_CTRL_BRAM_INIT_17" TYPE="STD_LOGIC_VECTOR" VALUE="0x0074011E0094211E0074011E0094211E0074011E0094211E0070111E0070011E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="775" NAME="C_CTRL_BRAM_INIT_16" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070801A0070001E0070001C0070001C0070001C0070001C0020401C0078001D"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="776" NAME="C_CTRL_BRAM_INIT_15" TYPE="STD_LOGIC_VECTOR" VALUE="0x00D8201C0078001C00D8201C0078001C00D8201C0078001C00D8201C0070101C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="777" NAME="C_CTRL_BRAM_INIT_14" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C007080180070001C0070001E0070001E0070001E0070400A0070001E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="778" NAME="C_CTRL_BRAM_INIT_13" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001F0070001E0070001E0070001E0070201E0074001E0094201E0074011E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="779" NAME="C_CTRL_BRAM_INIT_12" TYPE="STD_LOGIC_VECTOR" VALUE="0x0094211E0074011E0094211E0074011E0094211E0070111E0070011E0070801A"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="780" NAME="C_CTRL_BRAM_INIT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001C0070001C0070001C0070001C0020401C0078001D00D8201C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="781" NAME="C_CTRL_BRAM_INIT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0x0078001C00D8201C0070101C0070001C007080180070001C0070001E0070001E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="782" NAME="C_CTRL_BRAM_INIT_0F" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070400A0070001E0070001F0070001E0070001E0070001E0070201E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="783" NAME="C_CTRL_BRAM_INIT_0E" TYPE="STD_LOGIC_VECTOR" VALUE="0x0074001E0094201E0074011E0094211E0070111E0070011E0070801A0070001E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="784" NAME="C_CTRL_BRAM_INIT_0D" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0020401C0070001C0070001D0078001C00D8201C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="785" NAME="C_CTRL_BRAM_INIT_0C" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101C0070001C007080180070001C0070001E0070001E0070001E0070400A"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="786" NAME="C_CTRL_BRAM_INIT_0B" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001F0070001E0070001E0070001E0070201E0074001E0094201E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="787" NAME="C_CTRL_BRAM_INIT_0A" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070111E0070011E0070801A0070001E0070001C0070001C0070001C0020401C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="788" NAME="C_CTRL_BRAM_INIT_09" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001D0070001C0058201C0070101C0070001C007080180070001C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="789" NAME="C_CTRL_BRAM_INIT_08" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070001E0070400A0070001E0070001F0070001E0070001E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="790" NAME="C_CTRL_BRAM_INIT_07" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070201E0014201E0070101E0070011E0070801A0070001E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="791" NAME="C_CTRL_BRAM_INIT_06" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001C0070001C0020401C0070001C0070001D0070001C0058201C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="792" NAME="C_CTRL_BRAM_INIT_05" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101C0070001C007080180070001C0070001E0070001E0070001E0070400A"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="793" NAME="C_CTRL_BRAM_INIT_04" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001F0070001E0070001E0070001E0070001E0070001E0014201E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="794" NAME="C_CTRL_BRAM_INIT_03" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070101E0070011E0070801A0070001E0070001C0070001C0070001C0020401C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="795" NAME="C_CTRL_BRAM_INIT_02" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001C0070001D0070001C0058201C0070101C0070001C007080180070001C"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="796" NAME="C_CTRL_BRAM_INIT_01" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070001E0070400A0070001E0070001F0070001E0070001E"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="797" NAME="C_CTRL_BRAM_INIT_00" TYPE="STD_LOGIC_VECTOR" VALUE="0x0070001E0070001E0070001E0014201E0070101E0070011E0070801A0070001E"/>
        <PARAMETER MPD_INDEX="798" NAME="C_CTRL_BRAM_SRVAL" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000002FC"/>
        <PARAMETER MPD_INDEX="799" NAME="C_CTRL_BRAM_INITP_07" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER MPD_INDEX="800" NAME="C_CTRL_BRAM_INITP_06" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER MPD_INDEX="801" NAME="C_CTRL_BRAM_INITP_05" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER MPD_INDEX="802" NAME="C_CTRL_BRAM_INITP_04" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="803" NAME="C_CTRL_BRAM_INITP_03" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="804" NAME="C_CTRL_BRAM_INITP_02" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="805" NAME="C_CTRL_BRAM_INITP_01" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="806" NAME="C_CTRL_BRAM_INITP_00" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="674" NAME="SDMA3_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="675" NAME="SDMA3_Rx_IntOut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="mpmc_0_SDMA3_Rx_IntOut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="676" NAME="SDMA3_Tx_IntOut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="mpmc_0_SDMA3_Tx_IntOut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1674" NAME="MPMC_Clk0" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT2"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1677" NAME="MPMC_Clk_200MHz" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="1678" NAME="MPMC_Rst" SIGIS="RST" SIGNAME="sys_periph_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Peripheral_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="400000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="1679" NAME="MPMC_Clk_Mem" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT3"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="400000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1684" NAME="MPMC_Clk_Rd_Base" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0_nobuf_varphase">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT4"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="1695" NAME="MPMC_DCM_PSEN" SIGNAME="MPMC_DCM_PSEN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="PSEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="1696" NAME="MPMC_DCM_PSINCDEC" SIGNAME="MPMC_DCM_PSINCDEC">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="PSINCDEC"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="1697" NAME="MPMC_DCM_PSDONE" SIGNAME="MPMC_DCM_PSDONE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="PSDONE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="1739" NAME="DDR3_Clk" SIGIS="CLK" SIGNAME="fpga_0_mpmc_0_DDR3_Clk_pin" VECFORMULA="[C_MEM_CLK_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_Clk_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="1740" NAME="DDR3_Clk_n" SIGIS="CLK" SIGNAME="fpga_0_mpmc_0_DDR3_Clk_n_pin" VECFORMULA="[C_MEM_CLK_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_Clk_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="1741" NAME="DDR3_CE" SIGNAME="fpga_0_mpmc_0_DDR3_CE_pin" VECFORMULA="[C_MEM_CE_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_CE_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="1742" NAME="DDR3_CS_n" SIGNAME="fpga_0_mpmc_0_DDR3_CS_n_pin" VECFORMULA="[C_MEM_CS_N_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_CS_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="1743" NAME="DDR3_ODT" SIGNAME="fpga_0_mpmc_0_DDR3_ODT_pin" VECFORMULA="[C_MEM_ODT_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_ODT_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="1744" NAME="DDR3_RAS_n" SIGNAME="fpga_0_mpmc_0_DDR3_RAS_n_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_RAS_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="1745" NAME="DDR3_CAS_n" SIGNAME="fpga_0_mpmc_0_DDR3_CAS_n_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_CAS_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="1746" NAME="DDR3_WE_n" SIGNAME="fpga_0_mpmc_0_DDR3_WE_n_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_WE_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="19" MPD_INDEX="1747" MSB="2" NAME="DDR3_BankAddr" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_BankAddr_pin" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_BankAddr_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="20" MPD_INDEX="1748" MSB="12" NAME="DDR3_Addr" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_Addr_pin" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_Addr_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="31" LSB="0" MHS_INDEX="21" MPD_INDEX="1749" MSB="31" NAME="DDR3_DQ" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DQ_pin" VECFORMULA="[C_ECC_DATA_WIDTH  + C_MEM_DATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_DQ_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="22" MPD_INDEX="1750" MSB="3" NAME="DDR3_DM" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DM_pin" VECFORMULA="[C_ECC_DM_WIDTH    + C_MEM_DM_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_DM_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="1751" NAME="DDR3_Reset_n" SIGNAME="fpga_0_mpmc_0_DDR3_Reset_n_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_Reset_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MHS_INDEX="24" MPD_INDEX="1752" MSB="3" NAME="DDR3_DQS" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DQS_pin" VECFORMULA="[C_ECC_DQS_WIDTH   + C_MEM_DQS_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_DQS_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MHS_INDEX="25" MPD_INDEX="1753" MSB="3" NAME="DDR3_DQS_n" RIGHT="0" SIGNAME="fpga_0_mpmc_0_DDR3_DQS_n_pin" VECFORMULA="[C_ECC_DQS_WIDTH   + C_MEM_DQS_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_mpmc_0_DDR3_DQS_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="0" NAME="FSL0_M_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1" NAME="FSL0_M_Write" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="FSL0_M_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="3" NAME="FSL0_M_Control" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="4" NAME="FSL0_M_Full" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="FSL0_S_Clk" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="FSL0_S_Read" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="FSL0_S_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="8" NAME="FSL0_S_Control" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="9" NAME="FSL0_S_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="FSL0_B_M_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="FSL0_B_M_Write" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="FSL0_B_M_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="13" NAME="FSL0_B_M_Control" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="FSL0_B_M_Full" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="15" NAME="FSL0_B_S_Clk" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="16" NAME="FSL0_B_S_Read" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="FSL0_B_S_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="18" NAME="FSL0_B_S_Control" SIGNAME="__NOC__"/>
        <PORT BUS="XCL0_B" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="19" NAME="FSL0_B_S_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB0" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="20" NAME="SPLB0_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="21" NAME="SPLB0_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="22" MSB="0" NAME="SPLB0_PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="23" NAME="SPLB0_PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="24" NAME="SPLB0_PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="SPLB0_PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB0_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="26" NAME="SPLB0_PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="27" MSB="0" NAME="SPLB0_PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB0_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB0_PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="29" NAME="SPLB0_PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="30" NAME="SPLB0_PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="31" NAME="SPLB0_PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="32" NAME="SPLB0_PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="33" MSB="0" NAME="SPLB0_PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="SPLB0_PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="35" MSB="0" NAME="SPLB0_PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="36" NAME="SPLB0_PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="37" NAME="SPLB0_PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="SPLB0_PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="39" NAME="SPLB0_PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="SPLB0_PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="SPLB0_PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="42" MSB="0" NAME="SPLB0_PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="43" NAME="SPLB0_PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="44" NAME="SPLB0_PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="45" MSB="0" NAME="SPLB0_PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB0_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="46" NAME="SPLB0_Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB0_Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="48" NAME="SPLB0_Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="49" NAME="SPLB0_Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="50" NAME="SPLB0_Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="51" NAME="SPLB0_Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="52" NAME="SPLB0_Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="53" MSB="0" NAME="SPLB0_Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB0_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="54" MSB="0" NAME="SPLB0_Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="55" NAME="SPLB0_Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="56" NAME="SPLB0_Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="57" NAME="SPLB0_Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB0_Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="59" MSB="0" NAME="SPLB0_Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="60" MSB="0" NAME="SPLB0_Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB0" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="SPLB0_Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB0_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="SDMA0_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="63" NAME="SDMA0_Rx_IntOut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="64" NAME="SDMA0_Tx_IntOut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="SDMA0_RstOut" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="66" MSB="0" NAME="SDMA0_TX_D" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="67" MSB="0" NAME="SDMA0_TX_Rem" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="SDMA0_TX_SOF" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="SDMA0_TX_EOF" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="70" NAME="SDMA0_TX_SOP" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="SDMA0_TX_EOP" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="SDMA0_TX_Src_Rdy" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="73" NAME="SDMA0_TX_Dst_Rdy" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="74" MSB="0" NAME="SDMA0_RX_D" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="75" MSB="0" NAME="SDMA0_RX_Rem" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="76" NAME="SDMA0_RX_SOF" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="SDMA0_RX_EOF" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="SDMA0_RX_SOP" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="SDMA0_RX_EOP" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="SDMA0_RX_Src_Rdy" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_LL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="SDMA0_RX_Dst_Rdy" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="SDMA_CTRL0_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="SDMA_CTRL0_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="84" MSB="0" NAME="SDMA_CTRL0_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="SDMA_CTRL0_PLB_PAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="86" NAME="SDMA_CTRL0_PLB_SAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="SDMA_CTRL0_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SDMA_CTRL0_MID_WIDTH-1)]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="88" NAME="SDMA_CTRL0_PLB_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="89" MSB="0" NAME="SDMA_CTRL0_PLB_BE" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:((C_SDMA_CTRL0_DWIDTH/8)-1)]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="90" MSB="0" NAME="SDMA_CTRL0_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="SDMA_CTRL0_PLB_rdPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="92" NAME="SDMA_CTRL0_PLB_wrPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="93" NAME="SDMA_CTRL0_PLB_abort" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="94" NAME="SDMA_CTRL0_PLB_busLock" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="95" MSB="0" NAME="SDMA_CTRL0_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="96" MSB="0" NAME="SDMA_CTRL0_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="97" MSB="0" NAME="SDMA_CTRL0_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="SDMA_CTRL0_PLB_lockErr" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="SDMA_CTRL0_PLB_wrPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="100" MSB="0" NAME="SDMA_CTRL0_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="101" NAME="SDMA_CTRL0_PLB_rdPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="102" MSB="0" NAME="SDMA_CTRL0_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SDMA_CTRL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="103" MSB="0" NAME="SDMA_CTRL0_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
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          <CONNECTIONS>
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          </CONNECTIONS>
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          <CONNECTIONS>
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          <CONNECTIONS>
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          </CONNECTIONS>
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          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IXCL]" INSTANCE="microblaze_0" PORT="ICACHE_FSL_OUT_CONTROL"/>
          </CONNECTIONS>
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            <CONNECTION BUSINTERFACE="[IXCL]" INSTANCE="microblaze_0" PORT="ICACHE_FSL_IN_CLK"/>
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          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[IXCL]" INSTANCE="microblaze_0" PORT="ICACHE_FSL_IN_EXISTS"/>
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        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOF_n" DIR="O" MPD_INDEX="681" NAME="SDMA3_TX_EOF" SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOF_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="LlinkTemac0_EOF_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_SOP_n" DIR="O" MPD_INDEX="682" NAME="SDMA3_TX_SOP" SIGNAME="xps_ether_0_LLINK0_LL_Tx_SOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="LlinkTemac0_SOP_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOP_n" DIR="O" MPD_INDEX="683" NAME="SDMA3_TX_EOP" SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="LlinkTemac0_EOP_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_SrcRdy_n" DIR="O" MPD_INDEX="684" NAME="SDMA3_TX_Src_Rdy" SIGNAME="xps_ether_0_LLINK0_LL_Tx_SrcRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="LlinkTemac0_SRC_RDY_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_DstRdy_n" DIR="I" MPD_INDEX="685" NAME="SDMA3_TX_Dst_Rdy" SIGNAME="xps_ether_0_LLINK0_LL_Tx_DstRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_DST_RDY_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_Data" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="686" MSB="0" NAME="SDMA3_RX_D" RIGHT="31" SIGNAME="xps_ether_0_LLINK0_LL_Rx_Data" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_Rem" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="687" MSB="0" NAME="SDMA3_RX_Rem" RIGHT="3" SIGNAME="xps_ether_0_LLINK0_LL_Rx_Rem" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_REM"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOF_n" DIR="I" MPD_INDEX="688" NAME="SDMA3_RX_SOF" SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOF_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_SOF_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOF_n" DIR="I" MPD_INDEX="689" NAME="SDMA3_RX_EOF" SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOF_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_EOF_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOP_n" DIR="I" MPD_INDEX="690" NAME="SDMA3_RX_SOP" SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_SOP_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOP_n" DIR="I" MPD_INDEX="691" NAME="SDMA3_RX_EOP" SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_EOP_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_SrcRdy_n" DIR="I" MPD_INDEX="692" NAME="SDMA3_RX_Src_Rdy" SIGNAME="xps_ether_0_LLINK0_LL_Rx_SrcRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="Temac0Llink_SRC_RDY_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_LL3" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_DstRdy_n" DIR="O" MPD_INDEX="693" NAME="SDMA3_RX_Dst_Rdy" SIGNAME="xps_ether_0_LLINK0_LL_Rx_DstRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[LLINK0]" INSTANCE="xps_ether_0" PORT="LlinkTemac0_DST_RDY_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="694" NAME="SDMA_CTRL3_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="695" NAME="SDMA_CTRL3_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="696" MSB="0" NAME="SDMA_CTRL3_PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="697" NAME="SDMA_CTRL3_PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="698" NAME="SDMA_CTRL3_PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="699" MSB="0" NAME="SDMA_CTRL3_PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SDMA_CTRL3_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="700" NAME="SDMA_CTRL3_PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="701" MSB="0" NAME="SDMA_CTRL3_PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SDMA_CTRL3_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="702" MSB="0" NAME="SDMA_CTRL3_PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="703" NAME="SDMA_CTRL3_PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="704" NAME="SDMA_CTRL3_PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="705" NAME="SDMA_CTRL3_PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="706" NAME="SDMA_CTRL3_PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="707" MSB="0" NAME="SDMA_CTRL3_PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="708" MSB="0" NAME="SDMA_CTRL3_PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="709" MSB="0" NAME="SDMA_CTRL3_PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="710" NAME="SDMA_CTRL3_PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="711" NAME="SDMA_CTRL3_PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="712" MSB="0" NAME="SDMA_CTRL3_PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="713" NAME="SDMA_CTRL3_PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="714" MSB="0" NAME="SDMA_CTRL3_PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="715" MSB="0" NAME="SDMA_CTRL3_PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="716" MSB="0" NAME="SDMA_CTRL3_PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="717" NAME="SDMA_CTRL3_PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="718" NAME="SDMA_CTRL3_PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="719" MSB="0" NAME="SDMA_CTRL3_PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SDMA_CTRL3_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="720" NAME="SDMA_CTRL3_Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="721" MSB="0" NAME="SDMA_CTRL3_Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="722" NAME="SDMA_CTRL3_Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="723" NAME="SDMA_CTRL3_Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="724" NAME="SDMA_CTRL3_Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="725" NAME="SDMA_CTRL3_Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="726" NAME="SDMA_CTRL3_Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="727" MSB="0" NAME="SDMA_CTRL3_Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SDMA_CTRL3_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="728" MSB="0" NAME="SDMA_CTRL3_Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="729" NAME="SDMA_CTRL3_Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="730" NAME="SDMA_CTRL3_Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="731" NAME="SDMA_CTRL3_Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="732" MSB="0" NAME="SDMA_CTRL3_Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SDMA_CTRL3_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="733" MSB="0" NAME="SDMA_CTRL3_Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SDMA_CTRL3_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="734" MSB="0" NAME="SDMA_CTRL3_Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SDMA_CTRL3_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SDMA_CTRL3" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="735" MSB="0" NAME="SDMA_CTRL3_Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SDMA_CTRL3_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="736" MSB="31" NAME="PIM3_Addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="737" NAME="PIM3_AddrReq" SIGNAME="__NOC__"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="738" NAME="PIM3_AddrAck" SIGNAME="__NOC__"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="739" NAME="PIM3_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="740" MSB="3" NAME="PIM3_Size" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="741" NAME="PIM3_RdModWr" SIGNAME="__NOC__"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="742" MSB="63" NAME="PIM3_WrFIFO_Data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_PIM3_DATA_WIDTH-1):0]"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="743" MSB="7" NAME="PIM3_WrFIFO_BE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_PIM3_DATA_WIDTH/8-1):0]"/>
        <PORT BUS="MPMC_PIM3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="744" NAME="PIM3_WrFIFO_Push" SIGNAME="__NOC__"/>
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        <PORT BUS="VFBC7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="1597" MSB="3" NAME="VFBC7_Wd_Data_BE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_VFBC7_RDWD_DATA_WIDTH/8-1:0]"/>
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        <PORT BUS="MCB7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="1619" NAME="MCB7_wr_full" SIGNAME="__NOC__"/>
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        <PORT BUS="MPMC_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1635" NAME="MPMC_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
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        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1710" NAME="DDR_Clk_n" SIGIS="CLK" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CLK_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1711" NAME="DDR_CE" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CE_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1712" NAME="DDR_CS_n" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CS_N_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1713" NAME="DDR_RAS_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1714" NAME="DDR_CAS_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1715" NAME="DDR_WE_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="1716" MSB="2" NAME="DDR_BankAddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="12" LSB="0" MPD_INDEX="1717" MSB="12" NAME="DDR_Addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="1718" MSB="31" NAME="DDR_DQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_ECC_DATA_WIDTH  + C_MEM_DATA_WIDTH-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="1719" MSB="3" NAME="DDR_DM" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_ECC_DM_WIDTH    + C_MEM_DM_WIDTH-1:0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="1720" MSB="3" NAME="DDR_DQS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_ECC_DQS_WIDTH   + C_MEM_DQS_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1721" NAME="DDR_DQS_Div_O" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1722" NAME="DDR_DQS_Div_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1723" NAME="DDR2_Clk" SIGIS="CLK" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CLK_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1724" NAME="DDR2_Clk_n" SIGIS="CLK" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CLK_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1725" NAME="DDR2_CE" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CE_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1726" NAME="DDR2_CS_n" SIGNAME="__NOC__" VECFORMULA="[C_MEM_CS_N_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1727" NAME="DDR2_ODT" SIGNAME="__NOC__" VECFORMULA="[C_MEM_ODT_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1728" NAME="DDR2_RAS_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1729" NAME="DDR2_CAS_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1730" NAME="DDR2_WE_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="1731" MSB="2" NAME="DDR2_BankAddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="12" LSB="0" MPD_INDEX="1732" MSB="12" NAME="DDR2_Addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="1733" MSB="31" NAME="DDR2_DQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_ECC_DATA_WIDTH  + C_MEM_DATA_WIDTH-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="1734" MSB="3" NAME="DDR2_DM" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_ECC_DM_WIDTH    + C_MEM_DM_WIDTH-1:0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="1735" MSB="3" NAME="DDR2_DQS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_ECC_DQS_WIDTH   + C_MEM_DQS_WIDTH-1:0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="1736" MSB="3" NAME="DDR2_DQS_n" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_ECC_DQS_WIDTH   + C_MEM_DQS_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1737" NAME="DDR2_DQS_Div_O" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1738" NAME="DDR2_DQS_Div_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="12" LSB="0" MPD_INDEX="1754" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="1755" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1756" NAME="mcbx_dram_ras_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1757" NAME="mcbx_dram_cas_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1758" NAME="mcbx_dram_we_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1759" NAME="mcbx_dram_cke" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1760" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1761" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="1762" MSB="31" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_MEM_DATA_WIDTH-1:0]"/>
        <PORT DIR="IO" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" MPD_INDEX="1763" NAME="mcbx_dram_dqs" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" MPD_INDEX="1764" NAME="mcbx_dram_dqs_n" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" MPD_INDEX="1765" NAME="mcbx_dram_udqs" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" MPD_INDEX="1766" NAME="mcbx_dram_udqs_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1767" NAME="mcbx_dram_udm" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1768" NAME="mcbx_dram_ldm" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1769" NAME="mcbx_dram_odt" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="memory_0" IS_VALID="FALSE" MPD_INDEX="1770" NAME="mcbx_dram_ddr3_rst" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1771" NAME="selfrefresh_enter" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1772" NAME="selfrefresh_mode" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="1773" NAME="calib_recal" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" MPD_INDEX="1774" NAME="rzq" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IOS="memory_0" IS_THREE_STATE="FALSE" IS_VALID="FALSE" MPD_INDEX="1775" NAME="zio" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="0" NAME="XCL0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="1" NAME="XCL0_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL0_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="SPLB0" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB0_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB0_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="4" NAME="SDMA_LL0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA0_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA0_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="3" NAME="SDMA_CTRL0" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL0_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL0_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="5" NAME="MPMC_PIM0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM0_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM0_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM0_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="6" NAME="PPC440MC0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC0_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC0_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC0_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC0_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC0_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="7" NAME="VFBC0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC0_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC0_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="8" NAME="MCB0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB0_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB0_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB0_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_IXCL" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="9" NAME="XCL1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="10" NAME="XCL1_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL1_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="11" NAME="SPLB1" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB1_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB1_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="13" NAME="SDMA_LL1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA1_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA1_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="12" NAME="SDMA_CTRL1" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL1_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL1_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="14" NAME="MPMC_PIM1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM1_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM1_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM1_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="15" NAME="PPC440MC1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC1_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC1_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC1_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC1_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC1_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="16" NAME="VFBC1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC1_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC1_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="17" NAME="MCB1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB1_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB1_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB1_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_DXCL" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="18" NAME="XCL2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="19" NAME="XCL2_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL2_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="20" NAME="SPLB2" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB2_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB2_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="22" NAME="SDMA_LL2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA2_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA2_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="21" NAME="SDMA_CTRL2" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL2_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL2_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="23" NAME="MPMC_PIM2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM2_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM2_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM2_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="24" NAME="PPC440MC2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC2_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC2_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC2_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC2_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC2_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="25" NAME="VFBC2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC2_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC2_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="26" NAME="MCB2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB2_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB2_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB2_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="27" NAME="XCL3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="28" NAME="XCL3_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL3_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="29" NAME="SPLB3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB3_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB3_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="xps_ether_0_LLINK0" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="31" NAME="SDMA_LL3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA3_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA3_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="30" NAME="SDMA_CTRL3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL3_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL3_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="32" NAME="MPMC_PIM3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM3_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM3_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM3_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="33" NAME="PPC440MC3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC3_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC3_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC3_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC3_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC3_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="34" NAME="VFBC3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC3_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC3_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="35" NAME="MCB3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB3_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB3_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB3_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="36" NAME="XCL4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="37" NAME="XCL4_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL4_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="38" NAME="SPLB4" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB4_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB4_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="40" NAME="SDMA_LL4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA4_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA4_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="39" NAME="SDMA_CTRL4" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL4_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL4_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="41" NAME="MPMC_PIM4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM4_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM4_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM4_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="42" NAME="PPC440MC4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC4_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC4_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC4_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC4_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC4_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="43" NAME="VFBC4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC4_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC4_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="44" NAME="MCB4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB4_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB4_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB4_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="45" NAME="XCL5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="46" NAME="XCL5_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL5_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="47" NAME="SPLB5" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB5_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB5_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="49" NAME="SDMA_LL5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA5_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA5_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="48" NAME="SDMA_CTRL5" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL5_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL5_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="50" NAME="MPMC_PIM5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM5_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM5_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM5_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="51" NAME="PPC440MC5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC5_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC5_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC5_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC5_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC5_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="52" NAME="VFBC5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC5_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC5_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="53" NAME="MCB5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB5_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB5_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB5_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="54" NAME="XCL6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="55" NAME="XCL6_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL6_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="56" NAME="SPLB6" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB6_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB6_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="58" NAME="SDMA_LL6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA6_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA6_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="57" NAME="SDMA_CTRL6" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL6_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL6_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="59" NAME="MPMC_PIM6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM6_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM6_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM6_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="60" NAME="PPC440MC6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC6_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC6_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC6_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC6_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC6_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="61" NAME="VFBC6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC6_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC6_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="62" NAME="MCB6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB6_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB6_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB6_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="63" NAME="XCL7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="64" NAME="XCL7_B" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL7_B_M_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_B_M_Write"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_B_M_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_B_M_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_B_M_Full"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_B_S_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_B_S_Read"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_B_S_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_B_S_Control"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_B_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="65" NAME="SPLB7" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB7_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB7_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="67" NAME="SDMA_LL7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_RstOut"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_TX_D"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_TX_Rem"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_TX_SOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_TX_EOF"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_TX_SOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_TX_EOP"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_TX_Src_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_TX_Dst_Rdy"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_RX_D"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_RX_Rem"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_RX_SOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_RX_EOF"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_RX_SOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_RX_EOP"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA7_RX_Src_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA7_RX_Dst_Rdy"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="66" NAME="SDMA_CTRL7" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SDMA_CTRL7_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SDMA_CTRL7_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_NPI" IS_VALID="FALSE" MPD_INDEX="68" NAME="MPMC_PIM7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PIM7_Addr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_AddrReq"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_AddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_Size"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_RdModWr"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_WrFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_WrFIFO_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_WrFIFO_Push"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_RdFIFO_Data"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_RdFIFO_Pop"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_RdFIFO_RdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_WrFIFO_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_WrFIFO_AlmostFull"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_WrFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_RdFIFO_Empty"/>
            <PORTMAP DIR="I" PHYSICAL="PIM7_RdFIFO_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_RdFIFO_Latency"/>
            <PORTMAP DIR="O" PHYSICAL="PIM7_InitDone"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_PPC440MC" IS_VALID="FALSE" MPD_INDEX="69" NAME="PPC440MC7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCReadNotWrite"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCAddress"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCAddressValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCWriteData"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCWriteDataValid"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCByteEnable"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCBankConflict"/>
            <PORTMAP DIR="I" PHYSICAL="PPC440MC7_MIMCRowConflict"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC7_MCMIReadData"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC7_MCMIReadDataValid"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC7_MCMIReadDataErr"/>
            <PORTMAP DIR="O" PHYSICAL="PPC440MC7_MCMIAddrReadyToAccept"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_VFBC" IS_VALID="FALSE" MPD_INDEX="70" NAME="VFBC7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Cmd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Cmd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Cmd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Cmd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Cmd_End"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Cmd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Cmd_Almost_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Cmd_Idle"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Wd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Wd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Wd_Write"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Wd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Wd_Flush"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Wd_Data"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Wd_Data_BE"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Wd_Full"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Wd_Almost_Full"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Rd_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Rd_Reset"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Rd_Read"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Rd_End_Burst"/>
            <PORTMAP DIR="I" PHYSICAL="VFBC7_Rd_Flush"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Rd_Data"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Rd_Empty"/>
            <PORTMAP DIR="O" PHYSICAL="VFBC7_Rd_Almost_Empty"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MCB_PORT" IS_VALID="FALSE" MPD_INDEX="71" NAME="MCB7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MCB7_cmd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_cmd_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_cmd_instr"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_cmd_bl"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_cmd_byte_addr"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_cmd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_cmd_full"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_wr_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_wr_en"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_wr_mask"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_wr_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_wr_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_wr_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_wr_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_wr_underrun"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_wr_error"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_rd_clk"/>
            <PORTMAP DIR="I" PHYSICAL="MCB7_rd_en"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_rd_data"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_rd_full"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_rd_empty"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_rd_count"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_rd_overflow"/>
            <PORTMAP DIR="O" PHYSICAL="MCB7_rd_error"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="72" NAME="MPMC_CTRL" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_TAttribute"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="MPMC_CTRL_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="MPMC_CTRL_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="XIL_MEMORY_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="DDR3_Clk"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_Clk_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_CE"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_CS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_ODT"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_RAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_CAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_WE_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_BankAddr"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_Addr"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR3_DQ"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_DM"/>
            <PORTMAP DIR="O" PHYSICAL="DDR3_Reset_n"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR3_DQS"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR3_DQS_n"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_Clk"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_CE"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_CS_n"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_RAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_CAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_WE_n"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_BankAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_Addr"/>
            <PORTMAP DIR="IO" PHYSICAL="SDRAM_DQ"/>
            <PORTMAP DIR="O" PHYSICAL="SDRAM_DM"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_Clk"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_Clk_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_CE"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_CS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_RAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_CAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_WE_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_BankAddr"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_Addr"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_DQ"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_DM"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_DQS"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_DQS_Div_O"/>
            <PORTMAP DIR="I" PHYSICAL="DDR_DQS_Div_I"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_Clk"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_Clk_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_CE"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_CS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_ODT"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_RAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_CAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_WE_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_BankAddr"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_Addr"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR2_DQ"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_DM"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR2_DQS"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR2_DQS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR2_DQS_Div_O"/>
            <PORTMAP DIR="I" PHYSICAL="DDR2_DQS_Div_I"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
            <PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
            <PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
            <PORTMAP DIR="IO" PHYSICAL="rzq"/>
            <PORTMAP DIR="IO" PHYSICAL="zio"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="536870912" BASENAME="C_MPMC_BASEADDR" BASEVALUE="0x20000000" HIGHDECIMAL="805306367" HIGHNAME="C_MPMC_HIGHADDR" HIGHVALUE="0x2FFFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="268435456" SIZEABRV="256M">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL0"/>
            <SLAVE BUSINTERFACE="XCL0_B"/>
            <SLAVE BUSINTERFACE="SPLB0"/>
            <SLAVE BUSINTERFACE="SDMA_LL0"/>
            <SLAVE BUSINTERFACE="PPC440MC0"/>
            <SLAVE BUSINTERFACE="VFBC0"/>
            <SLAVE BUSINTERFACE="XCL1"/>
            <SLAVE BUSINTERFACE="XCL1_B"/>
            <SLAVE BUSINTERFACE="SPLB1"/>
            <SLAVE BUSINTERFACE="SDMA_LL1"/>
            <SLAVE BUSINTERFACE="PPC440MC1"/>
            <SLAVE BUSINTERFACE="VFBC1"/>
            <SLAVE BUSINTERFACE="XCL2"/>
            <SLAVE BUSINTERFACE="XCL2_B"/>
            <SLAVE BUSINTERFACE="SPLB2"/>
            <SLAVE BUSINTERFACE="SDMA_LL2"/>
            <SLAVE BUSINTERFACE="PPC440MC2"/>
            <SLAVE BUSINTERFACE="VFBC2"/>
            <SLAVE BUSINTERFACE="XCL3"/>
            <SLAVE BUSINTERFACE="XCL3_B"/>
            <SLAVE BUSINTERFACE="SPLB3"/>
            <SLAVE BUSINTERFACE="SDMA_LL3"/>
            <SLAVE BUSINTERFACE="PPC440MC3"/>
            <SLAVE BUSINTERFACE="VFBC3"/>
            <SLAVE BUSINTERFACE="XCL4"/>
            <SLAVE BUSINTERFACE="XCL4_B"/>
            <SLAVE BUSINTERFACE="SPLB4"/>
            <SLAVE BUSINTERFACE="SDMA_LL4"/>
            <SLAVE BUSINTERFACE="PPC440MC4"/>
            <SLAVE BUSINTERFACE="VFBC4"/>
            <SLAVE BUSINTERFACE="XCL5"/>
            <SLAVE BUSINTERFACE="XCL5_B"/>
            <SLAVE BUSINTERFACE="SPLB5"/>
            <SLAVE BUSINTERFACE="SDMA_LL5"/>
            <SLAVE BUSINTERFACE="PPC440MC5"/>
            <SLAVE BUSINTERFACE="VFBC5"/>
            <SLAVE BUSINTERFACE="XCL6"/>
            <SLAVE BUSINTERFACE="XCL6_B"/>
            <SLAVE BUSINTERFACE="SPLB6"/>
            <SLAVE BUSINTERFACE="SDMA_LL6"/>
            <SLAVE BUSINTERFACE="PPC440MC6"/>
            <SLAVE BUSINTERFACE="VFBC6"/>
            <SLAVE BUSINTERFACE="XCL7"/>
            <SLAVE BUSINTERFACE="XCL7_B"/>
            <SLAVE BUSINTERFACE="SPLB7"/>
            <SLAVE BUSINTERFACE="SDMA_LL7"/>
            <SLAVE BUSINTERFACE="PPC440MC7"/>
            <SLAVE BUSINTERFACE="VFBC7"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MPMC_SW_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_MPMC_SW_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U"/>
        <MEMRANGE BASEDECIMAL="2329870336" BASENAME="C_SDMA_CTRL_BASEADDR" BASEVALUE="0x8ADF0000" HIGHDECIMAL="2329935871" HIGHNAME="C_SDMA_CTRL_HIGHADDR" HIGHVALUE="0x8ADFFFFF" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL0"/>
            <SLAVE BUSINTERFACE="SDMA_CTRL1"/>
            <SLAVE BUSINTERFACE="SDMA_CTRL2"/>
            <SLAVE BUSINTERFACE="SDMA_CTRL3"/>
            <SLAVE BUSINTERFACE="SDMA_CTRL4"/>
            <SLAVE BUSINTERFACE="SDMA_CTRL5"/>
            <SLAVE BUSINTERFACE="SDMA_CTRL6"/>
            <SLAVE BUSINTERFACE="SDMA_CTRL7"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MPMC_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_MPMC_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="MPMC_CTRL"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM0_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM0_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL0"/>
            <SLAVE BUSINTERFACE="XCL0_B"/>
            <SLAVE BUSINTERFACE="SPLB0"/>
            <SLAVE BUSINTERFACE="SDMA_LL0"/>
            <SLAVE BUSINTERFACE="PPC440MC0"/>
            <SLAVE BUSINTERFACE="VFBC0"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL0_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL0_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL0"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM1_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM1_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL1"/>
            <SLAVE BUSINTERFACE="XCL1_B"/>
            <SLAVE BUSINTERFACE="SPLB1"/>
            <SLAVE BUSINTERFACE="SDMA_LL1"/>
            <SLAVE BUSINTERFACE="PPC440MC1"/>
            <SLAVE BUSINTERFACE="VFBC1"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL1_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL1_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL1"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM2_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM2_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL2"/>
            <SLAVE BUSINTERFACE="XCL2_B"/>
            <SLAVE BUSINTERFACE="SPLB2"/>
            <SLAVE BUSINTERFACE="SDMA_LL2"/>
            <SLAVE BUSINTERFACE="PPC440MC2"/>
            <SLAVE BUSINTERFACE="VFBC2"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL2_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL2_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL2"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM3_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM3_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL3"/>
            <SLAVE BUSINTERFACE="XCL3_B"/>
            <SLAVE BUSINTERFACE="SPLB3"/>
            <SLAVE BUSINTERFACE="SDMA_LL3"/>
            <SLAVE BUSINTERFACE="PPC440MC3"/>
            <SLAVE BUSINTERFACE="VFBC3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL3_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL3_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM4_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM4_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL4"/>
            <SLAVE BUSINTERFACE="XCL4_B"/>
            <SLAVE BUSINTERFACE="SPLB4"/>
            <SLAVE BUSINTERFACE="SDMA_LL4"/>
            <SLAVE BUSINTERFACE="PPC440MC4"/>
            <SLAVE BUSINTERFACE="VFBC4"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL4_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL4_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL4"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM5_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM5_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL5"/>
            <SLAVE BUSINTERFACE="XCL5_B"/>
            <SLAVE BUSINTERFACE="SPLB5"/>
            <SLAVE BUSINTERFACE="SDMA_LL5"/>
            <SLAVE BUSINTERFACE="PPC440MC5"/>
            <SLAVE BUSINTERFACE="VFBC5"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL5_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL5_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL5"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM6_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM6_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL6"/>
            <SLAVE BUSINTERFACE="XCL6_B"/>
            <SLAVE BUSINTERFACE="SPLB6"/>
            <SLAVE BUSINTERFACE="SDMA_LL6"/>
            <SLAVE BUSINTERFACE="PPC440MC6"/>
            <SLAVE BUSINTERFACE="VFBC6"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL6_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL6_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL6"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_PIM7_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_PIM7_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="XCL7"/>
            <SLAVE BUSINTERFACE="XCL7_B"/>
            <SLAVE BUSINTERFACE="SPLB7"/>
            <SLAVE BUSINTERFACE="SDMA_LL7"/>
            <SLAVE BUSINTERFACE="PPC440MC7"/>
            <SLAVE BUSINTERFACE="VFBC7"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SDMA_CTRL7_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SDMA_CTRL7_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDMA_CTRL7"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="8"/>
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="9"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="1.01.a" INSTANCE="xps_sysace_0" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="xps_sysace">
      <DESCRIPTION TYPE="SHORT">XPS System ACE Interface Controller(Compact Flash)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_sysace_v1_01_a/doc/xps_sysace.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x83600000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8360ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="C_MEM_WIDTH" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>Width of System ACE Data Bus </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="sysace_0" IS_INSTANTIATED="TRUE" LEFT="6" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="6" NAME="SysACE_MPA" RIGHT="0" SIGNAME="fpga_0_xps_sysace_0_SysACE_MPA_pin" VECFORMULA="[6:0]">
          <DESCRIPTION>Address Input</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_sysace_0_SysACE_MPA_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="43" NAME="SysACE_CLK" SIGNAME="fpga_0_xps_sysace_0_SysACE_CLK_pin">
          <DESCRIPTION>Clock Input</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_sysace_0_SysACE_CLK_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="44" NAME="SysACE_MPIRQ" SIGNAME="fpga_0_xps_sysace_0_SysACE_MPIRQ_pin">
          <DESCRIPTION>Active high Interrupt Output</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_sysace_0_SysACE_MPIRQ_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="48" NAME="SysACE_CEN" SIGNAME="fpga_0_xps_sysace_0_SysACE_CEN_pin">
          <DESCRIPTION>Active LOW Chip Enable</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_sysace_0_SysACE_CEN_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="49" NAME="SysACE_OEN" SIGNAME="fpga_0_xps_sysace_0_SysACE_OEN_pin">
          <DESCRIPTION>Active LOW Output Enable</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_sysace_0_SysACE_OEN_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="50" NAME="SysACE_WEN" SIGNAME="fpga_0_xps_sysace_0_SysACE_WEN_pin">
          <DESCRIPTION>Active LOW Write Enable</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_sysace_0_SysACE_WEN_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="51" NAME="SysACE_IRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xps_sysace_0_SysACE_IRQ">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="sysace_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="7" LSB="0" MHS_INDEX="7" MPD_INDEX="52" MSB="7" NAME="SysACE_MPD" RIGHT="0" SIGNAME="fpga_0_xps_sysace_0_SysACE_MPD_pin" TRI_I="SysACE_MPD_I" TRI_O="SysACE_MPD_O" TRI_T="SysACE_MPD_T" VECFORMULA="[(C_MEM_WIDTH-1):0]">
          <DESCRIPTION>Data Input/Output</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_sysace_0_SysACE_MPD_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="sysace_0" LEFT="7" LSB="0" MPD_INDEX="45" MSB="7" NAME="SysACE_MPD_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="sysace_0" LEFT="7" LSB="0" MPD_INDEX="46" MSB="7" NAME="SysACE_MPD_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="sysace_0" LEFT="7" LSB="0" MPD_INDEX="47" MSB="7" NAME="SysACE_MPD_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="sysace_0" TYPE="XIL_SYSACE_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SysACE_MPA"/>
            <PORTMAP DIR="I" PHYSICAL="SysACE_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="SysACE_MPIRQ"/>
            <PORTMAP DIR="O" PHYSICAL="SysACE_CEN"/>
            <PORTMAP DIR="O" PHYSICAL="SysACE_OEN"/>
            <PORTMAP DIR="O" PHYSICAL="SysACE_WEN"/>
            <PORTMAP DIR="IO" PHYSICAL="SysACE_MPD"/>
            <PORTMAP DIR="I" PHYSICAL="SysACE_MPD_I"/>
            <PORTMAP DIR="O" PHYSICAL="SysACE_MPD_O"/>
            <PORTMAP DIR="O" PHYSICAL="SysACE_MPD_T"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2204106752" BASENAME="C_BASEADDR" BASEVALUE="0x83600000" HIGHDECIMAL="2204172287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8360ffff" MEMTYPE="REGISTER" MINSIZE="0x80" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="5"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="2.03.a" INSTANCE="xps_ether_0" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="xps_ll_temac">
      <DESCRIPTION TYPE="SHORT">XPS LocalLink Tri-mode Ethernet MAC</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ll_temac_v2_03_a/doc/xps_ll_temac.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO EXPIRESON="Jan-30-2016" ICON_NAME="ps_pay_core_4" STATE="Hardware Evaluation" TYPE="Hardware_Evaluation"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="C_NUM_IDELAYCTRL" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>C_NUM_IDELAYCTRL</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_IDELAYCTRL_LOC" TYPE="STRING" VALUE="IDELAYCTRL_X2Y1">
          <DESCRIPTION>C_IDELAYCTRL_LOC</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx">
          <DESCRIPTION>Device Sub Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_RESERVED" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_RESERVED</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>C_FAMILY</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x88F00000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x88F7FFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_INCLUDE_IO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Include IO and BUFG as Needed for the PHY Interface Selected</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_PHY_TYPE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Physical Interface Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="15" NAME="C_TEMAC1_ENABLED" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable TEMAC 1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TEMAC0_TXFIFO" TYPE="INTEGER" VALUE="4096">
          <DESCRIPTION>TX FIFO Depth of TEMAC0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="17" NAME="C_TEMAC0_RXFIFO" TYPE="INTEGER" VALUE="4096">
          <DESCRIPTION>RX FIFO Depth of TEMAC0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_TEMAC1_TXFIFO" TYPE="INTEGER" VALUE="4096">
          <DESCRIPTION>TX FIFO Depth of TEMAC1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TEMAC1_RXFIFO" TYPE="INTEGER" VALUE="4096">
          <DESCRIPTION>RX FIFO Depth of TEMAC1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="20" NAME="C_BUS2CORE_CLK_RATIO" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Ratio of PLB Bus Clock to Core Clock</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="21" NAME="C_TEMAC_TYPE" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>Type of TEMAC</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_TEMAC0_TXCSUM" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable TX Checksum Offload for TEMAC0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="23" NAME="C_TEMAC0_RXCSUM" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable RX Checksum Offload for TEMAC0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_TEMAC1_TXCSUM" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable TX Checksum Offload for TEMAC1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_TEMAC1_RXCSUM" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable RX Checksum Offload for TEMAC1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="26" NAME="C_TEMAC0_PHYADDR" TYPE="std_logic_vector" VALUE="0b00001">
          <DESCRIPTION>PHY Address for TEMAC 0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="27" NAME="C_TEMAC1_PHYADDR" TYPE="std_logic_vector" VALUE="0b00010">
          <DESCRIPTION>PHY Address for TEMAC 1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="28" NAME="C_TEMAC0_TXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_TXVLAN_TRAN</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_TEMAC0_RXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_RXVLAN_TRAN</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_TEMAC1_TXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_TXVLAN_TRAN</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="31" NAME="C_TEMAC1_RXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_RXVLAN_TRAN</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="32" NAME="C_TEMAC0_TXVLAN_TAG" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_TXVLAN_TAG</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="33" NAME="C_TEMAC0_RXVLAN_TAG" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_RXVLAN_TAG</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="34" NAME="C_TEMAC1_TXVLAN_TAG" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_TXVLAN_TAG</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="35" NAME="C_TEMAC1_RXVLAN_TAG" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_RXVLAN_TAG</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="36" NAME="C_TEMAC0_TXVLAN_STRP" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_TXVLAN_STRP</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="37" NAME="C_TEMAC0_RXVLAN_STRP" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_RXVLAN_STRP</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="38" NAME="C_TEMAC1_TXVLAN_STRP" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_TXVLAN_STRP</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="39" NAME="C_TEMAC1_RXVLAN_STRP" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_RXVLAN_STRP</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="40" NAME="C_TEMAC0_MCAST_EXTEND" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_MCAST_EXTEND</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="41" NAME="C_TEMAC1_MCAST_EXTEND" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_MCAST_EXTEND</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="42" NAME="C_TEMAC0_STATS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_STATS</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="43" NAME="C_TEMAC1_STATS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_STATS</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="44" NAME="C_TEMAC0_AVB" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC0_AVB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="45" NAME="C_TEMAC1_AVB" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_TEMAC1_AVB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_SIMULATION" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>C_SIMULATION</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="TemacIntc0_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xps_ether_0_TemacIntc0_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="TemacPhy_RST_n" SIGNAME="fpga_0_xps_ether_0_TemacPhy_RST_n_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_TemacPhy_RST_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="125000000" DIR="I" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="GTX_CLK_0" SIGIS="CLK" SIGNAME="clk_125_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT1"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="REFCLK" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT2"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="51" NAME="LlinkTemac0_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="94" NAME="MII_TX_CLK_0" SIGNAME="fpga_0_xps_ether_0_MII_TX_CLK_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_MII_TX_CLK_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="temacif_0" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="6" MPD_INDEX="103" MSB="7" NAME="GMII_TXD_0" RIGHT="0" SIGNAME="fpga_0_xps_ether_0_GMII_TXD_0_pin" VECFORMULA="[7:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_TXD_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="104" NAME="GMII_TX_EN_0" SIGNAME="fpga_0_xps_ether_0_GMII_TX_EN_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_TX_EN_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="105" NAME="GMII_TX_ER_0" SIGNAME="fpga_0_xps_ether_0_GMII_TX_ER_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_TX_ER_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="106" NAME="GMII_TX_CLK_0" SIGNAME="fpga_0_xps_ether_0_GMII_TX_CLK_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_TX_CLK_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="temacif_0" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="10" MPD_INDEX="107" MSB="7" NAME="GMII_RXD_0" RIGHT="0" SIGNAME="fpga_0_xps_ether_0_GMII_RXD_0_pin" VECFORMULA="[7:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_RXD_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="108" NAME="GMII_RX_DV_0" SIGNAME="fpga_0_xps_ether_0_GMII_RX_DV_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_RX_DV_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="109" NAME="GMII_RX_ER_0" SIGNAME="fpga_0_xps_ether_0_GMII_RX_ER_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_RX_ER_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="110" NAME="GMII_RX_CLK_0" SIGNAME="fpga_0_xps_ether_0_GMII_RX_CLK_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_GMII_RX_CLK_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="temacif_0" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="139" NAME="MDC_0" SIGNAME="fpga_0_xps_ether_0_MDC_0_pin">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_MDC_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="temacif_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="15" MPD_INDEX="206" NAME="MDIO_0" SIGNAME="fpga_0_xps_ether_0_MDIO_0_pin" TRI_I="MDIO_0_I" TRI_O="MDIO_0_O" TRI_T="MDIO_0_T">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_ether_0_MDIO_0_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="1" NAME="TemacIntc1_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="4" NAME="MGTCLK_P" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="5" NAME="MGTCLK_N" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="7" NAME="DCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="8" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="9" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="10" NAME="Core_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="13" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="14" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="15" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="16" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="17" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="18" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="19" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="20" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="21" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="23" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="24" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="25" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="26" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="27" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="28" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="29" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="30" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="32" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="33" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="34" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="35" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="37" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="38" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="39" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="40" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="41" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="42" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="44" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="45" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="46" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="47" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="48" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="49" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="50" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_RST_ACK" DIR="I" MPD_INDEX="52" NAME="LlinkTemac0_RST" SIGNAME="xps_ether_0_LLINK0_LL_RST_ACK">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RstOut"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_SOP_n" DIR="I" MPD_INDEX="53" NAME="LlinkTemac0_SOP_n" SIGNAME="xps_ether_0_LLINK0_LL_Tx_SOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_SOP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOP_n" DIR="I" MPD_INDEX="54" NAME="LlinkTemac0_EOP_n" SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_EOP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_SOF_n" DIR="I" MPD_INDEX="55" NAME="LlinkTemac0_SOF_n" SIGNAME="xps_ether_0_LLINK0_LL_Tx_SOF_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_SOF"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOF_n" DIR="I" MPD_INDEX="56" NAME="LlinkTemac0_EOF_n" SIGNAME="xps_ether_0_LLINK0_LL_Tx_EOF_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_EOF"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_Rem" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="LlinkTemac0_REM" RIGHT="3" SIGNAME="xps_ether_0_LLINK0_LL_Tx_Rem" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_Rem"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_Data" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="58" MSB="0" NAME="LlinkTemac0_Data" RIGHT="31" SIGNAME="xps_ether_0_LLINK0_LL_Tx_Data" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_D"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_SrcRdy_n" DIR="I" MPD_INDEX="59" NAME="LlinkTemac0_SRC_RDY_n" SIGNAME="xps_ether_0_LLINK0_LL_Tx_SrcRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_Src_Rdy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Tx_DstRdy_n" DIR="O" MPD_INDEX="60" NAME="Temac0Llink_DST_RDY_n" SIGNAME="xps_ether_0_LLINK0_LL_Tx_DstRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_TX_Dst_Rdy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOP_n" DIR="O" MPD_INDEX="61" NAME="Temac0Llink_SOP_n" SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_SOP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOP_n" DIR="O" MPD_INDEX="62" NAME="Temac0Llink_EOP_n" SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOP_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_EOP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOF_n" DIR="O" MPD_INDEX="63" NAME="Temac0Llink_SOF_n" SIGNAME="xps_ether_0_LLINK0_LL_Rx_SOF_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_SOF"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOF_n" DIR="O" MPD_INDEX="64" NAME="Temac0Llink_EOF_n" SIGNAME="xps_ether_0_LLINK0_LL_Rx_EOF_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_EOF"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_Rem" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="65" MSB="0" NAME="Temac0Llink_REM" RIGHT="3" SIGNAME="xps_ether_0_LLINK0_LL_Rx_Rem" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_Rem"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_Data" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="66" MSB="0" NAME="Temac0Llink_Data" RIGHT="31" SIGNAME="xps_ether_0_LLINK0_LL_Rx_Data" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_D"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_SrcRdy_n" DIR="O" MPD_INDEX="67" NAME="Temac0Llink_SRC_RDY_n" SIGNAME="xps_ether_0_LLINK0_LL_Rx_SrcRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_Src_Rdy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="LLINK0" DEF_SIGNAME="xps_ether_0_LLINK0_LL_Rx_DstRdy_n" DIR="I" MPD_INDEX="68" NAME="LlinkTemac0_DST_RDY_n" SIGNAME="xps_ether_0_LLINK0_LL_Rx_DstRdy_n">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SDMA_LL3]" INSTANCE="mpmc_0" PORT="SDMA3_RX_Dst_Rdy"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="69" NAME="LlinkTemac1_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="70" NAME="LlinkTemac1_RST" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="71" NAME="LlinkTemac1_SOP_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="72" NAME="LlinkTemac1_EOP_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="73" NAME="LlinkTemac1_SOF_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="74" NAME="LlinkTemac1_EOF_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="75" MSB="0" NAME="LlinkTemac1_REM" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="76" MSB="0" NAME="LlinkTemac1_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="77" NAME="LlinkTemac1_SRC_RDY_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="78" NAME="Temac1Llink_DST_RDY_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="79" NAME="Temac1Llink_SOP_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="80" NAME="Temac1Llink_EOP_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="81" NAME="Temac1Llink_SOF_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="82" NAME="Temac1Llink_EOF_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="83" MSB="0" NAME="Temac1Llink_REM" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="84" MSB="0" NAME="Temac1Llink_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="85" NAME="Temac1Llink_SRC_RDY_n" SIGNAME="__NOC__"/>
        <PORT BUS="LLINK1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="86" NAME="LlinkTemac1_DST_RDY_n" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="temacif_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="87" MSB="3" NAME="MII_TXD_0" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="88" NAME="MII_TX_EN_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="89" NAME="MII_TX_ER_0" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="temacif_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="90" MSB="3" NAME="MII_RXD_0" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="91" NAME="MII_RX_DV_0" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="92" NAME="MII_RX_ER_0" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="93" NAME="MII_RX_CLK_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="95" MSB="3" NAME="MII_TXD_1" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="96" NAME="MII_TX_EN_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="97" NAME="MII_TX_ER_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="98" MSB="3" NAME="MII_RXD_1" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="99" NAME="MII_RX_DV_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="100" NAME="MII_RX_ER_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="101" NAME="MII_RX_CLK_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="102" NAME="MII_TX_CLK_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="111" MSB="7" NAME="GMII_TXD_1" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="112" NAME="GMII_TX_EN_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="113" NAME="GMII_TX_ER_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="114" NAME="GMII_TX_CLK_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="GMII_RXD_1" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="116" NAME="GMII_RX_DV_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="117" NAME="GMII_RX_ER_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="118" NAME="GMII_RX_CLK_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="119" NAME="TXP_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="120" NAME="TXN_0" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="121" NAME="RXP_0" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="122" NAME="RXN_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="123" NAME="TXP_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="124" NAME="TXN_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="125" NAME="RXP_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="126" NAME="RXN_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="temacif_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="127" MSB="3" NAME="RGMII_TXD_0" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="128" NAME="RGMII_TX_CTL_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="129" NAME="RGMII_TXC_0" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="temacif_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="130" MSB="3" NAME="RGMII_RXD_0" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="131" NAME="RGMII_RX_CTL_0" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" IS_VALID="FALSE" MPD_INDEX="132" NAME="RGMII_RXC_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="133" MSB="3" NAME="RGMII_TXD_1" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="134" NAME="RGMII_TX_CTL_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="135" NAME="RGMII_TXC_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="136" MSB="3" NAME="RGMII_RXD_1" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="137" NAME="RGMII_RX_CTL_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="138" NAME="RGMII_RXC_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="140" NAME="MDC_1" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="host_mii_rdy" DIR="I" MPD_INDEX="141" NAME="HostMiimRdy" SIGNAME="host_mii_rdy">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="host_rd_data" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="142" MSB="31" NAME="HostRdData" RIGHT="0" SIGNAME="host_rd_data" VECFORMULA="[31:0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="host_mii_sel" DIR="O" MPD_INDEX="143" NAME="HostMiimSel" SIGNAME="host_mii_sel">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="host_req" DIR="O" MPD_INDEX="144" NAME="HostReq" SIGNAME="host_req">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="host_addr" DIR="O" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="145" MSB="9" NAME="HostAddr" RIGHT="0" SIGNAME="host_addr" VECFORMULA="[9:0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="host_emac1_sel" DIR="O" MPD_INDEX="146" NAME="HostEmac1Sel" SIGNAME="host_emac1_sel">
          <CONNECTIONS/>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="147" NAME="Temac0AvbTxClk" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="148" NAME="Temac0AvbTxClkEn" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="149" NAME="Temac0AvbRxClk" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="150" NAME="Temac0AvbRxClkEn" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="151" MSB="7" NAME="Avb2Mac0TxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="152" NAME="Avb2Mac0TxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="153" NAME="Avb2Mac0TxUnderrun" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="154" NAME="Mac02AvbTxAck" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="155" MSB="7" NAME="Mac02AvbRxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="156" NAME="Mac02AvbRxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="157" NAME="Mac02AvbRxFrameGood" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="158" NAME="Mac02AvbRxFrameBad" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="159" MSB="7" NAME="Temac02AvbTxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="160" NAME="Temac02AvbTxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="161" NAME="Temac02AvbTxUnderrun" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="162" NAME="Avb2Temac0TxAck" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="163" MSB="7" NAME="Avb2Temac0RxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="164" NAME="Avb2Temac0RxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="165" NAME="Avb2Temac0RxFrameGood" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="166" NAME="Avb2Temac0RxFrameBad" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="167" NAME="Temac1AvbTxClk" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="168" NAME="Temac1AvbTxClkEn" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="169" NAME="Temac1AvbRxClk" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="170" NAME="Temac1AvbRxClkEn" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="171" MSB="7" NAME="Avb2Mac1TxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="172" NAME="Avb2Mac1TxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="173" NAME="Avb2Mac1TxUnderrun" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="174" NAME="Mac12AvbTxAck" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="175" MSB="7" NAME="Mac12AvbRxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="176" NAME="Mac12AvbRxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="177" NAME="Mac12AvbRxFrameGood" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="178" NAME="Mac12AvbRxFrameBad" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="179" MSB="7" NAME="Temac12AvbTxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="180" NAME="Temac12AvbTxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="181" NAME="Temac12AvbTxUnderrun" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="182" NAME="Avb2Temac1TxAck" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="183" MSB="7" NAME="Avb2Temac1RxData" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="184" NAME="Avb2Temac1RxDataValid" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="185" NAME="Avb2Temac1RxFrameGood" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="186" NAME="Avb2Temac1RxFrameBad" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="187" NAME="TxClientClk_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="188" NAME="ClientTxStat_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="189" NAME="ClientTxStatsVld_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="190" NAME="ClientTxStatsByteVld_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="191" NAME="RxClientClk_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="192" MSB="6" NAME="ClientRxStats_0" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[6:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="193" NAME="ClientRxStatsVld_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="194" NAME="ClientRxStatsByteVld_0" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="195" NAME="TxClientClk_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="196" NAME="ClientTxStat_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="197" NAME="ClientTxStatsVld_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="198" NAME="ClientTxStatsByteVld_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="199" NAME="RxClientClk_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="200" MSB="6" NAME="ClientRxStats_1" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[6:0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="201" NAME="ClientRxStatsVld_1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="202" NAME="ClientRxStatsByteVld_1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_0" MPD_INDEX="203" NAME="MDIO_0_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_0" MPD_INDEX="204" NAME="MDIO_0_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_0" MPD_INDEX="205" NAME="MDIO_0_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="207" NAME="MDIO_1_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="208" NAME="MDIO_1_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="temacif_1" IS_VALID="FALSE" MPD_INDEX="209" NAME="MDIO_1_T" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IOS="temacif_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="210" NAME="MDIO_1" SIGNAME="__NOC__" TRI_I="MDIO_1_I" TRI_O="MDIO_1_O" TRI_T="MDIO_1_T"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="xps_ether_0_LLINK0" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="LLINK0" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_RST"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_SOP_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_EOP_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_SOF_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_EOF_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_REM"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_Data"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_SRC_RDY_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_DST_RDY_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_SOP_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_EOP_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_SOF_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_EOF_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_REM"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_Data"/>
            <PORTMAP DIR="O" PHYSICAL="Temac0Llink_SRC_RDY_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac0_DST_RDY_n"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_LL_DMA" IS_VALID="FALSE" MPD_INDEX="2" NAME="LLINK1" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_RST"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_SOP_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_EOP_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_SOF_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_EOF_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_REM"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_Data"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_SRC_RDY_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_DST_RDY_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_SOP_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_EOP_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_SOF_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_EOF_n"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_REM"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_Data"/>
            <PORTMAP DIR="O" PHYSICAL="Temac1Llink_SRC_RDY_n"/>
            <PORTMAP DIR="I" PHYSICAL="LlinkTemac1_DST_RDY_n"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="temacif_0" TYPE="XIL_TEMAC_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="TemacPhy_RST_n"/>
            <PORTMAP DIR="I" PHYSICAL="GTX_CLK_0"/>
            <PORTMAP DIR="I" PHYSICAL="MII_TX_CLK_0"/>
            <PORTMAP DIR="O" PHYSICAL="GMII_TXD_0"/>
            <PORTMAP DIR="O" PHYSICAL="GMII_TX_EN_0"/>
            <PORTMAP DIR="O" PHYSICAL="GMII_TX_ER_0"/>
            <PORTMAP DIR="O" PHYSICAL="GMII_TX_CLK_0"/>
            <PORTMAP DIR="I" PHYSICAL="GMII_RXD_0"/>
            <PORTMAP DIR="I" PHYSICAL="GMII_RX_DV_0"/>
            <PORTMAP DIR="I" PHYSICAL="GMII_RX_ER_0"/>
            <PORTMAP DIR="I" PHYSICAL="GMII_RX_CLK_0"/>
            <PORTMAP DIR="O" PHYSICAL="MDC_0"/>
            <PORTMAP DIR="IO" PHYSICAL="MDIO_0"/>
            <PORTMAP DIR="I" PHYSICAL="MGTCLK_P"/>
            <PORTMAP DIR="I" PHYSICAL="MGTCLK_N"/>
            <PORTMAP DIR="O" PHYSICAL="MII_TXD_0"/>
            <PORTMAP DIR="O" PHYSICAL="MII_TX_EN_0"/>
            <PORTMAP DIR="O" PHYSICAL="MII_TX_ER_0"/>
            <PORTMAP DIR="I" PHYSICAL="MII_RXD_0"/>
            <PORTMAP DIR="I" PHYSICAL="MII_RX_DV_0"/>
            <PORTMAP DIR="I" PHYSICAL="MII_RX_ER_0"/>
            <PORTMAP DIR="I" PHYSICAL="MII_RX_CLK_0"/>
            <PORTMAP DIR="O" PHYSICAL="TXP_0"/>
            <PORTMAP DIR="O" PHYSICAL="TXN_0"/>
            <PORTMAP DIR="I" PHYSICAL="RXP_0"/>
            <PORTMAP DIR="I" PHYSICAL="RXN_0"/>
            <PORTMAP DIR="O" PHYSICAL="RGMII_TXD_0"/>
            <PORTMAP DIR="O" PHYSICAL="RGMII_TX_CTL_0"/>
            <PORTMAP DIR="O" PHYSICAL="RGMII_TXC_0"/>
            <PORTMAP DIR="I" PHYSICAL="RGMII_RXD_0"/>
            <PORTMAP DIR="I" PHYSICAL="RGMII_RX_CTL_0"/>
            <PORTMAP DIR="I" PHYSICAL="RGMII_RXC_0"/>
            <PORTMAP DIR="I" PHYSICAL="MDIO_0_I"/>
            <PORTMAP DIR="O" PHYSICAL="MDIO_0_O"/>
            <PORTMAP DIR="O" PHYSICAL="MDIO_0_T"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="1" NAME="temacif_1" TYPE="XIL_TEMAC_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="TXP_1"/>
            <PORTMAP DIR="O" PHYSICAL="TXN_1"/>
            <PORTMAP DIR="I" PHYSICAL="RXP_1"/>
            <PORTMAP DIR="I" PHYSICAL="RXN_1"/>
            <PORTMAP DIR="O" PHYSICAL="MDC_1"/>
            <PORTMAP DIR="I" PHYSICAL="MDIO_1_I"/>
            <PORTMAP DIR="O" PHYSICAL="MDIO_1_O"/>
            <PORTMAP DIR="O" PHYSICAL="MDIO_1_T"/>
            <PORTMAP DIR="IO" PHYSICAL="MDIO_1"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2297430016" BASENAME="C_BASEADDR" BASEVALUE="0x88F00000" HIGHDECIMAL="2297954303" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x88F7FFFF" MEMTYPE="REGISTER" MINSIZE="0x80000" SIZE="524288" SIZEABRV="512K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="4"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="1.02.a" INSTANCE="xps_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="xps_timer">
      <DESCRIPTION TYPE="SHORT">XPS Timer/Counter</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Timer counter with PLBV46 interface</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_timer_v1_02_a/doc/xps_timer.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
          <DESCRIPTION>Count Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Only One Timer is present</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x8AEF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8AEFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="xps_timer_0_Interrupt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
          <DESCRIPTION>Capture Trig 0</DESCRIPTION>
        </PORT>
        <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
          <DESCRIPTION>Capture Trig 1</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
          <DESCRIPTION>Generate Out 0</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
          <DESCRIPTION>Generate Out 1</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
          <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
        </PORT>
        <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="7" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="8" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:C_SPLB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="10" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="11" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="12" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="13" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="16" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="17" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="18" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="19" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="20" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="21" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="22" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="23" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="24" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="25" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="27" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="29" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:C_SPLB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="30" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="31" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="32" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="33" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="34" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="36" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="37" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="38" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="39" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="40" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="44" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="45" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="47" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="48" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2330918912" BASENAME="C_BASEADDR" BASEVALUE="0x8AEF0000" HIGHDECIMAL="2330984447" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8AEFFFFF" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="10"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="3.00.a" INSTANCE="xps_uart_0" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="PERIPHERAL" MODTYPE="xps_uart16550">
      <DESCRIPTION TYPE="SHORT">XPS UART (16550-style)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">PLBV46 16550/450 UART (Universal Asynchronous Receiver/Transmitter)</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_uart16550_v3_00_a/doc/xps_uart16550.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x89FF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x89FFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="C_IS_A_16550" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Uart Configuration </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_HAS_EXTERNAL_XIN" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>External XIN is Present</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_HAS_EXTERNAL_RCLK" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>External RCLK is Present</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_EXTERNAL_XIN_CLK_HZ" TYPE="INTEGER" VALUE="25000000">
          <DESCRIPTION>XIN Clock Frequency</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="54" NAME="sin" SIGNAME="fpga_0_xps_uart_0_sin_pin">
          <DESCRIPTION>Serial Data Input</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_uart_0_sin_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="55" NAME="sout" SIGNAME="fpga_0_xps_uart_0_sout_pin">
          <DESCRIPTION>Serial Data Output</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_uart_0_sout_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="56" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xps_uart_0_IP2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:C_SPLB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:C_SPLB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="42" NAME="baudoutN" SIGNAME="__NOC__">
          <DESCRIPTION>Transmitter Clock</DESCRIPTION>
        </PORT>
        <PORT DIR="I" IOS="uart_0" MPD_INDEX="43" NAME="ctsN" SIGNAME="__NOC__">
          <DESCRIPTION>Clear To Send</DESCRIPTION>
        </PORT>
        <PORT DIR="I" IOS="uart_0" MPD_INDEX="44" NAME="dcdN" SIGNAME="__NOC__">
          <DESCRIPTION>Data Carrier Detect</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" MPD_INDEX="45" NAME="ddis" SIGNAME="__NOC__">
          <DESCRIPTION>Driver disable</DESCRIPTION>
        </PORT>
        <PORT DIR="I" IOS="uart_0" MPD_INDEX="46" NAME="dsrN" SIGNAME="__NOC__">
          <DESCRIPTION>Data Set Ready</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" MPD_INDEX="47" NAME="dtrN" SIGNAME="__NOC__">
          <DESCRIPTION>Data Terminal Ready</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" MPD_INDEX="48" NAME="out1N" SIGNAME="__NOC__">
          <DESCRIPTION>User Controlled Output</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" MPD_INDEX="49" NAME="out2N" SIGNAME="__NOC__">
          <DESCRIPTION>User Controlled Output</DESCRIPTION>
        </PORT>
        <PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="50" NAME="rclk" SIGIS="CLK" SIGNAME="__NOC__">
          <DESCRIPTION>Receiver 16x Clock</DESCRIPTION>
        </PORT>
        <PORT DIR="I" IOS="uart_0" MPD_INDEX="51" NAME="riN" SIGNAME="__NOC__">
          <DESCRIPTION>Ring Indicator</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" MPD_INDEX="52" NAME="rtsN" SIGNAME="__NOC__">
          <DESCRIPTION>Request To Send</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" MPD_INDEX="53" NAME="rxrdyN" SIGNAME="__NOC__">
          <DESCRIPTION>DMA Control Signal</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" MPD_INDEX="57" NAME="txrdyN" SIGNAME="__NOC__">
          <DESCRIPTION>DMA Control Signal</DESCRIPTION>
        </PORT>
        <PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="58" NAME="xin" SIGIS="CLK" SIGNAME="__NOC__">
          <DESCRIPTION>Baudrate Generator Reference Clock</DESCRIPTION>
        </PORT>
        <PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="59" NAME="xout" SIGNAME="__NOC__">
          <DESCRIPTION>Inverted XIN</DESCRIPTION>
        </PORT>
        <PORT DIR="I" MPD_INDEX="60" NAME="Freeze" SIGNAME="__NOC__">
          <DESCRIPTION>Freeze UART</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="sin"/>
            <PORTMAP DIR="O" PHYSICAL="sout"/>
            <PORTMAP DIR="I" PHYSICAL="ctsN"/>
            <PORTMAP DIR="I" PHYSICAL="dcdN"/>
            <PORTMAP DIR="O" PHYSICAL="ddis"/>
            <PORTMAP DIR="I" PHYSICAL="dsrN"/>
            <PORTMAP DIR="O" PHYSICAL="dtrN"/>
            <PORTMAP DIR="O" PHYSICAL="out1N"/>
            <PORTMAP DIR="O" PHYSICAL="out2N"/>
            <PORTMAP DIR="I" PHYSICAL="rclk"/>
            <PORTMAP DIR="I" PHYSICAL="riN"/>
            <PORTMAP DIR="O" PHYSICAL="rtsN"/>
            <PORTMAP DIR="O" PHYSICAL="rxrdyN"/>
            <PORTMAP DIR="O" PHYSICAL="txrdyN"/>
            <PORTMAP DIR="I" PHYSICAL="xin"/>
            <PORTMAP DIR="O" PHYSICAL="xout"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2315190272" BASENAME="C_BASEADDR" BASEVALUE="0x89FF0000" HIGHDECIMAL="2315255807" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x89FFFFFF" MEMTYPE="REGISTER" MINSIZE="0x2000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="3"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="xps_mch_emc_0_CE_inverter" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="IP" MODTYPE="util_vector_logic">
      <DESCRIPTION TYPE="SHORT">Utility Vector Logic</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'Simple logic functions, and, or, xor, not.'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/util_vector_logic_v1_00_a/doc/util_vector_logic.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="C_OPERATION" TYPE="string" VALUE="not">
          <DESCRIPTION>Type of Vector Operation To Perform </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_SIZE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Size of The Vector </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="Op1" SIGNAME="net_bsbassign0" VECFORMULA="[0:C_SIZE-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[emc_0]" INSTANCE="xps_mch_emc_0" PORT="Mem_CEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="Res" SIGNAME="fpga_0_xps_mch_emc_0_CE_inverter_Res_pin" VECFORMULA="[0:C_SIZE-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_mch_emc_0_CE_inverter_Res_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="1" NAME="Op2" SIGNAME="__NOC__" VECFORMULA="[0:C_SIZE-1]"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="1.01.a" INSTANCE="PCIe_Diff_Clk" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="IP" MODTYPE="util_ds_buf">
      <DESCRIPTION TYPE="SHORT">Differential Signaling IO Buffer</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Differential Signaling IO Buffer Primitive</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/util_ds_buf_v1_01_a/doc/util_ds_buf.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="C_BUF_TYPE" TYPE="STRING" VALUE="IBUFDSGTXE"/>
        <PARAMETER MPD_INDEX="1" NAME="C_SIZE" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="IBUF_DS_P" SIGNAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" VECFORMULA="[0:(C_SIZE-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="IBUF_DS_N" SIGNAME="fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" VECFORMULA="[0:(C_SIZE-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="IBUF_OUT" SIGNAME="net_bsbassign1" VECFORMULA="[0:(C_SIZE-1)]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[pcie_0]" INSTANCE="PCIe_Bridge" PORT="REFCLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="3" NAME="OBUF_IN" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
        <PORT DIR="O" MPD_INDEX="4" NAME="OBUF_DS_P" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
        <PORT DIR="O" MPD_INDEX="5" NAME="OBUF_DS_N" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
        <PORT DIR="IO" IS_THREE_STATE="FALSE" MPD_INDEX="6" NAME="IOBUF_DS_P" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
        <PORT DIR="IO" IS_THREE_STATE="FALSE" MPD_INDEX="7" NAME="IOBUF_DS_N" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
        <PORT DIR="I" MPD_INDEX="8" NAME="IOBUF_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
        <PORT DIR="I" MPD_INDEX="9" NAME="IOBUF_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
        <PORT DIR="O" MPD_INDEX="10" NAME="IOBUF_IO_O" SIGNAME="__NOC__" VECFORMULA="[0:(C_SIZE-1)]"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="2.03.a" INSTANCE="xps_central_dma_0" IPTYPE="PERIPHERAL" MHS_INDEX="20" MODCLASS="PERIPHERAL" MODTYPE="xps_central_dma">
      <DESCRIPTION TYPE="SHORT">XPS Central DMA Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Simple Direct Memory Access (DMA) services for PLBV46</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_central_dma_v2_03_a/doc/xps_central_dma.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_FIFO_DEPTH" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>FIFO Depth</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_RD_BURST_SIZE" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>Read Burst Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_WR_BURST_SIZE" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>Write Burst Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x8ACF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8ACFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_MPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Master</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_MPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Address Bus Width of Master PLB Bus</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_MPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>Data Bus Width of Master PLB Bus</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="15" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="44" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xps_central_dma_0_IP2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="2" NAME="MPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_MPLB_Rst" DIR="I" MPD_INDEX="3" NAME="MPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_MPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="MPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="SPLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:(C_SPLB_AWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="5" MSB="0" NAME="SPLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="SPLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="7" NAME="SPLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="8" NAME="SPLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="9" NAME="SPLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="10" NAME="SPLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="11" MSB="0" NAME="SPLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="12" NAME="SPLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="13" NAME="SPLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="14" NAME="SPLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="15" MSB="0" NAME="SPLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="SPLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="17" MSB="0" NAME="SPLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="18" NAME="SPLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="19" MSB="0" NAME="SPLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="20" NAME="SPLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="21" NAME="SPLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="22" NAME="SPLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="23" NAME="SPLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="SPLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="SPLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="SPLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="27" MSB="0" NAME="SPLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="28" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="29" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="30" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="31" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="32" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="33" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="34" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="35" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="36" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="37" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="38" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="39" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="42" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="43" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="45" NAME="MPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MAddrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="MPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="47" NAME="MPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="48" NAME="MPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MTimeout"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="49" NAME="MPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="50" NAME="MPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="51" NAME="MPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="52" NAME="MPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="53" MSB="0" NAME="MPLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:(C_MPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="54" MSB="0" NAME="MPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="55" NAME="MPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="56" NAME="MPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MRdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="57" NAME="MPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="58" NAME="MPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MWrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="59" NAME="M_request" SIGNAME="mb_plb_M_request">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_request"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="60" MSB="0" NAME="M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_priority"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="61" NAME="M_busLock" SIGNAME="mb_plb_M_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="62" NAME="M_RNW" SIGNAME="mb_plb_M_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:((C_MPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="64" MSB="0" NAME="M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="65" MSB="0" NAME="M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="66" MSB="0" NAME="M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="67" MSB="0" NAME="M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="68" NAME="M_lockErr" SIGNAME="mb_plb_M_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_abort" DIR="O" MPD_INDEX="69" NAME="M_abort" SIGNAME="mb_plb_M_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="70" MSB="0" NAME="M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="71" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:(C_MPLB_AWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="72" MSB="0" NAME="M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:(C_MPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="73" NAME="M_wrBurst" SIGNAME="mb_plb_M_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="74" NAME="M_rdBurst" SIGNAME="mb_plb_M_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="M_rdBurst"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="MPLB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="MPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MAddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MSSize"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MRearbitrate"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MTimeout"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MBusy"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MWrErr"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MIRQ"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MRdDBus"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MRdWdAddr"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MRdDAck"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MRdBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MWrDAck"/>
            <PORTMAP DIR="I" PHYSICAL="MPLB_MWrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="M_request"/>
            <PORTMAP DIR="O" PHYSICAL="M_priority"/>
            <PORTMAP DIR="O" PHYSICAL="M_busLock"/>
            <PORTMAP DIR="O" PHYSICAL="M_RNW"/>
            <PORTMAP DIR="O" PHYSICAL="M_BE"/>
            <PORTMAP DIR="O" PHYSICAL="M_MSize"/>
            <PORTMAP DIR="O" PHYSICAL="M_size"/>
            <PORTMAP DIR="O" PHYSICAL="M_type"/>
            <PORTMAP DIR="O" PHYSICAL="M_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="M_lockErr"/>
            <PORTMAP DIR="O" PHYSICAL="M_abort"/>
            <PORTMAP DIR="O" PHYSICAL="M_UABus"/>
            <PORTMAP DIR="O" PHYSICAL="M_ABus"/>
            <PORTMAP DIR="O" PHYSICAL="M_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="M_wrBurst"/>
            <PORTMAP DIR="O" PHYSICAL="M_rdBurst"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2328821760" BASENAME="C_BASEADDR" BASEVALUE="0x8ACF0000" HIGHDECIMAL="2328887295" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8ACFFFFF" MEMTYPE="REGISTER" MINSIZE="0x40" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="7"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="4.03.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="21" MODCLASS="IP" MODTYPE="clock_generator">
      <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_03_a/doc/clock_generator.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6vlx240t">
          <DESCRIPTION>Device</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="ff1156">
          <DESCRIPTION>Package</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1">
          <DESCRIPTION>Speed Grade</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000">
          <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="100000000">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="MMCM0">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="125000000">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="200000000">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="MMCM0">
          <DESCRIPTION>Required Group </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Varaible Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="400000000">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="MMCM0">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="400000000">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="MMCM0">
          <DESCRIPTION>Required Group </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION> Varaible Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION> Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION> Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Clock Deskew</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="MMCM0">
          <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
        <PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="94" NAME="C_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="95" NAME="C_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="96" NAME="C_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="97" NAME="C_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="98" NAME="C_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="99" NAME="C_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="100" NAME="C_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="101" NAME="C_CLKOUT7_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="102" NAME="C_CLKOUT8_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="103" NAME="C_CLKOUT9_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="104" NAME="C_CLKOUT10_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="105" NAME="C_CLKOUT11_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="106" NAME="C_CLKOUT12_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="107" NAME="C_CLKOUT13_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="108" NAME="C_CLKOUT14_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="109" NAME="C_CLKOUT15_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER MPD_INDEX="110" NAME="C_CLK_GEN" VALUE="UPDATE"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="dcm_clk_s">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_clk_1_sys_clk_p_pin"/>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_clk_1_sys_clk_n_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DPLB:IPLB:DLMB:ILMB]" INSTANCE="microblaze_0" PORT="CLK"/>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_Clk"/>
            <CONNECTION INSTANCE="ilmb" PORT="LMB_CLK"/>
            <CONNECTION INSTANCE="dlmb" PORT="LMB_CLK"/>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="dlmb_cntlr" PORT="LMB_Clk"/>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="ilmb_cntlr" PORT="LMB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_3" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_4" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_1" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_2" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_mch_emc_0" PORT="MCH_SPLB_Clk"/>
            <CONNECTION INSTANCE="xps_mch_emc_0" PORT="RdClk"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="PCIe_Bridge" PORT="MPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="PCIe_Bridge" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB0]" INSTANCE="mpmc_0" PORT="SPLB0_Clk"/>
            <CONNECTION INSTANCE="mpmc_0" PORT="SDMA3_Clk"/>
            <CONNECTION BUSINTERFACE="[SDMA_CTRL3]" INSTANCE="mpmc_0" PORT="SDMA_CTRL3_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_sysace_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_ether_0" PORT="SPLB_Clk"/>
            <CONNECTION INSTANCE="xps_ether_0" PORT="LlinkTemac0_CLK"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_timer_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_uart_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_central_dma_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[MPLB]" INSTANCE="xps_central_dma_0" PORT="MPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mdm_0" PORT="SPLB_Clk"/>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Slowest_sync_clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_intc_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_gpio_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="xps_iic_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_reg_0" PORT="SPLB_Clk"/>
            <CONNECTION BUSINTERFACE="[SPLB]" INSTANCE="mbref_mio_0" PORT="SPLB_Clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="125000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clk_125_0000MHz">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[temacif_0]" INSTANCE="xps_ether_0" PORT="GTX_CLK_0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_Clk0"/>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_Clk_200MHz"/>
            <CONNECTION INSTANCE="xps_ether_0" PORT="REFCLK"/>
            <CONNECTION INSTANCE="clock_generator_0" PORT="PSCLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="400000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_Clk_Mem"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="400000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="clk_400_0000MHzMMCM0_nobuf_varphase">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_Clk_Rd_Base"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="clk_200_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="20" NAME="PSEN" SIGNAME="MPMC_DCM_PSEN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_DCM_PSEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="MPMC_DCM_PSINCDEC">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_DCM_PSINCDEC"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="22" NAME="PSDONE" SIGNAME="MPMC_DCM_PSDONE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_DCM_PSDONE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="sys_rst_s">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_rst_1_sys_rst_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="24" NAME="LOCKED" SIGNAME="Dcm_all_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Dcm_locked"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="2.00.b" INSTANCE="mdm_0" IPTYPE="PERIPHERAL" MHS_INDEX="22" MODCLASS="DEBUG" MODTYPE="mdm">
      <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8FFF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8FFFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable JTAG UART </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>AXI Address Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>AXI Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
          <DESCRIPTION>AXI4LITE protocal</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGIS="RST" SIGNAME="Debug_SYS_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="MB_Debug_Sys_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0" PORT="EXT_BRK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0" PORT="EXT_NM_BRK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGIS="CLK" SIGNAME="microblaze_0_mdm_bus_Dbg_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DBG_CLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDI">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DBG_TDI"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDO">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DBG_TDO"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" VECFORMULA="[0:7]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DBG_REG_EN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Capture">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DBG_CAPTURE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Shift">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DBG_SHIFT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Update">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DBG_UPDATE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGIS="RST" SIGNAME="microblaze_0_mdm_bus_Debug_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DEBUG]" INSTANCE="microblaze_0" PORT="DEBUG_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGIS="RST" SIGNAME="bscan_reset">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGIS="CLK" SIGNAME="bscan_drck1">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1">
          <CONNECTIONS/>
        </PORT>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_mdm_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
            <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2415853568" BASENAME="C_BASEADDR" BASEVALUE="0x8FFF0000" HIGHDECIMAL="2415919103" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8FFFFFFF" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="23" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
      <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx">
          <DESCRIPTION>Device Subfamily</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>External Reset Active High </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="sys_rst_s">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_rst_1_sys_rst_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="Debug_SYS_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mdm_0" PORT="Debug_SYS_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="Dcm_all_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="LOCKED"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="mb_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0" PORT="MB_RESET"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="sys_bus_reset" VECFORMULA="[0:C_NUM_BUS_RST-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SYS_Rst"/>
            <CONNECTION INSTANCE="ilmb" PORT="SYS_RST"/>
            <CONNECTION INSTANCE="dlmb" PORT="SYS_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="sys_periph_reset" VECFORMULA="[0:C_NUM_PERP_RST-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mpmc_0" PORT="MPMC_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="internal_reset_request">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="xps_gpio_0" PORT="GPIO_IO_O"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
        <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
      </IOINTERFACES>
    </MODULE>
    <MODULE HWVERSION="2.01.a" INSTANCE="xps_intc_0" IPTYPE="PERIPHERAL" MHS_INDEX="24" MODCLASS="INTERRUPT_CNTLR" MODTYPE="xps_intc">
      <DESCRIPTION TYPE="SHORT">XPS Interrupt Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">intc core attached to the PLBV46</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_01_a/doc/xps_intc.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="1" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x8AFF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="2" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8AFFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="11">
          <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111100000000001">
          <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
          <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
          <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support IPR </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support SIE </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support CIE </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="17" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support IVR </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="10" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="10" NAME="Intr" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="mbref_mio_0_IP2INTC_Irpt &amp; mbref_reg_0_IP2INTC_Irpt &amp; xps_iic_0_IIC2INTC_Irpt &amp; xps_uart_0_IP2INTC_Irpt &amp; xps_ether_0_TemacIntc0_Irpt &amp; xps_sysace_0_SysACE_IRQ &amp; PCIe_Bridge_IP2INTC_Irpt &amp; xps_central_dma_0_IP2INTC_Irpt &amp; mpmc_0_SDMA3_Rx_IntOut &amp; mpmc_0_SDMA3_Tx_IntOut &amp; xps_timer_0_Interrupt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
          <SIGNALS>
            <SIGNAL NAME="mbref_mio_0_IP2INTC_Irpt"/>
            <SIGNAL NAME="mbref_reg_0_IP2INTC_Irpt"/>
            <SIGNAL NAME="xps_iic_0_IIC2INTC_Irpt"/>
            <SIGNAL NAME="xps_uart_0_IP2INTC_Irpt"/>
            <SIGNAL NAME="xps_ether_0_TemacIntc0_Irpt"/>
            <SIGNAL NAME="xps_sysace_0_SysACE_IRQ"/>
            <SIGNAL NAME="PCIe_Bridge_IP2INTC_Irpt"/>
            <SIGNAL NAME="xps_central_dma_0_IP2INTC_Irpt"/>
            <SIGNAL NAME="mpmc_0_SDMA3_Rx_IntOut"/>
            <SIGNAL NAME="mpmc_0_SDMA3_Tx_IntOut"/>
            <SIGNAL NAME="xps_timer_0_Interrupt"/>
          </SIGNALS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="mbref_mio_0_IP2INTC_Irpt &amp; mbref_reg_0_IP2INTC_Irpt &amp; xps_iic_0_IIC2INTC_Irpt &amp; xps_uart_0_IP2INTC_Irpt &amp; xps_ether_0_TemacIntc0_Irpt &amp; xps_sysace_0_SysACE_IRQ &amp; PCIe_Bridge_IP2INTC_Irpt &amp; xps_central_dma_0_IP2INTC_Irpt &amp; mpmc_0_SDMA3_Rx_IntOut &amp; mpmc_0_SDMA3_Tx_IntOut &amp; xps_timer_0_Interrupt"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="43" NAME="Irq" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_Interrupt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0" PORT="INTERRUPT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="4" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="6" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="8" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="9" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="10" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="32" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="36" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2331967488" BASENAME="C_BASEADDR" BASEVALUE="0x8AFF0000" HIGHDECIMAL="2332033023" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8AFFFFFF" MEMTYPE="REGISTER" MINSIZE="0x20" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
        <SOURCE INSTANCE="mbref_mio_0" PRIORITY="0" SIGNAME="mbref_mio_0_IP2INTC_Irpt"/>
        <SOURCE INSTANCE="mbref_reg_0" PRIORITY="1" SIGNAME="mbref_reg_0_IP2INTC_Irpt"/>
        <SOURCE INSTANCE="xps_iic_0" PRIORITY="2" SIGNAME="xps_iic_0_IIC2INTC_Irpt"/>
        <SOURCE INSTANCE="xps_uart_0" PRIORITY="3" SIGNAME="xps_uart_0_IP2INTC_Irpt"/>
        <SOURCE INSTANCE="xps_ether_0" PRIORITY="4" SIGNAME="xps_ether_0_TemacIntc0_Irpt"/>
        <SOURCE INSTANCE="xps_sysace_0" PRIORITY="5" SIGNAME="xps_sysace_0_SysACE_IRQ"/>
        <SOURCE INSTANCE="PCIe_Bridge" PRIORITY="6" SIGNAME="PCIe_Bridge_IP2INTC_Irpt"/>
        <SOURCE INSTANCE="xps_central_dma_0" PRIORITY="7" SIGNAME="xps_central_dma_0_IP2INTC_Irpt"/>
        <SOURCE INSTANCE="mpmc_0" PRIORITY="8" SIGNAME="mpmc_0_SDMA3_Rx_IntOut"/>
        <SOURCE INSTANCE="mpmc_0" PRIORITY="9" SIGNAME="mpmc_0_SDMA3_Tx_IntOut"/>
        <SOURCE INSTANCE="xps_timer_0" PRIORITY="10" SIGNAME="xps_timer_0_Interrupt"/>
        <TARGET INSTANCE="microblaze_0"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="xps_gpio_0" IPTYPE="PERIPHERAL" MHS_INDEX="25" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80FF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x80FFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IOS="gpio_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="44" NAME="GPIO_IO_O" SIGNAME="internal_reset_request" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Aux_Reset_In"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="gpio_0" MPD_INDEX="43" NAME="GPIO_IO_I" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" IOS="gpio_0" MPD_INDEX="45" NAME="GPIO_IO_T" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IOS="gpio_0" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" IOS="gpio_0" IS_THREE_STATE="TRUE" MPD_INDEX="49" NAME="GPIO_IO" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2164195328" BASENAME="C_BASEADDR" BASEVALUE="0x80FF0000" HIGHDECIMAL="2164260863" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80FFFFFF" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.03.a" INSTANCE="xps_iic_0" IPTYPE="PERIPHERAL" MHS_INDEX="26" MODCLASS="PERIPHERAL" MODTYPE="xps_iic">
      <DESCRIPTION TYPE="SHORT">XPS IIC Interface</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">PLBV46 interface to Philips I2C bus v2.1</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="/opt/Xilinx/13.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_iic_v2_03_a/doc/xps_iic.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="C_IIC_FREQ" TYPE="INTEGER" VALUE="100000">
          <DESCRIPTION>Output Frequency of SCL Signal</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_TEN_BIT_ADR" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use 10-bit Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_GPO_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Width of GPIO</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_CLK_FREQ" TYPE="INTEGER" VALUE="100000000">
          <DESCRIPTION>PLBv46 Bus Clock Frequency</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SCL_INERTIAL_DELAY" TYPE="INTEGER" VALUE="5">
          <DESCRIPTION>Width of glitches removed on SCL input</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SDA_INERTIAL_DELAY" TYPE="INTEGER" VALUE="5">
          <DESCRIPTION>Width of glitches removed on SDA input</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="4" MPD_INDEX="6" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80EF0000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="5" MPD_INDEX="7" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x80EFFFFF">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="0" MPD_INDEX="50" NAME="Sda" SIGNAME="fpga_0_xps_iic_0_Sda_pin" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
          <DESCRIPTION>IIC Serial Data</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_iic_0_Sda_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="1" MPD_INDEX="51" NAME="Scl" SIGNAME="fpga_0_xps_iic_0_Scl_pin" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
          <DESCRIPTION>IIC Serial Clock</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="fpga_0_xps_iic_0_Scl_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="IIC2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xps_iic_0_IIC2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="iic_0" MPD_INDEX="0" NAME="Sda_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="1" NAME="Sda_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="2" NAME="Sda_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="iic_0" MPD_INDEX="3" NAME="Scl_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="4" NAME="Scl_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="5" NAME="Scl_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="6" NAME="Gpo" SIGNAME="__NOC__" VECFORMULA="[(32-C_GPO_WIDTH):(32-1)]">
          <DESCRIPTION>IIC General Purpose Output</DESCRIPTION>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="8" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="9" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="10" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="12" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="13" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="14" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="15" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="17" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="18" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="19" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="20" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="21" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="22" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="23" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="24" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="25" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="26" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="27" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="28" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="29" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="32" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="33" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="34" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="36" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="37" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="38" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="39" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="41" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="42" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="43" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="44" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="45" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="47" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="48" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="49" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="iic_0" TYPE="XIL_IIC_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="Sda"/>
            <PORTMAP DIR="IO" PHYSICAL="Scl"/>
            <PORTMAP DIR="I" PHYSICAL="Sda_I"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_O"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_T"/>
            <PORTMAP DIR="I" PHYSICAL="Scl_I"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_O"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_T"/>
            <PORTMAP DIR="O" PHYSICAL="Gpo"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2163146752" BASENAME="C_BASEADDR" BASEVALUE="0x80EF0000" HIGHDECIMAL="2163212287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x80EFFFFF" MEMTYPE="REGISTER" MINSIZE="0x00200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="2"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="mbref_reg_0" IPTYPE="PERIPHERAL" MHS_INDEX="27" MODCLASS="PERIPHERAL" MODTYPE="plbv46_mbref_reg">
      <DESCRIPTION TYPE="SHORT">plbv46_mbref_reg</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">MicroBlaze References simple register bank for PLB v4.6.</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80800000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8080FFFF"/>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="10000"/>
        <PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_DPHASE_TIMER" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="mbref_reg_0_IP2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2155872256" BASENAME="C_BASEADDR" BASEVALUE="0x80800000" HIGHDECIMAL="2155937791" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8080FFFF" MEMTYPE="REGISTER" MINSIZE="0x400" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="1"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="mbref_mio_0" IPTYPE="PERIPHERAL" MHS_INDEX="28" MODCLASS="PERIPHERAL" MODTYPE="plbv46_mbref_mio">
      <DESCRIPTION TYPE="SHORT">plbv46_mbref_mio</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">MicroBlaze References simple memory bank for PLB v4.6.</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x80400000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8040FFFF"/>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="10000"/>
        <PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_DPHASE_TIMER" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_FAMILY" TYPE="STRING" VALUE="virtex6"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="C_MEM0_BASEADDR" TYPE="std_logic_vector" VALUE="0x80410000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="C_MEM0_HIGHADDR" TYPE="std_logic_vector" VALUE="0x804101FF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="C_MEM1_BASEADDR" TYPE="std_logic_vector" VALUE="0x80411000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="16" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x804111FF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="17" NAME="C_MEM2_BASEADDR" TYPE="std_logic_vector" VALUE="0x80412000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="18" NAME="C_MEM2_HIGHADDR" TYPE="std_logic_vector" VALUE="0x804121FF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="19" NAME="C_MEM3_BASEADDR" TYPE="std_logic_vector" VALUE="0x80413000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="20" NAME="C_MEM3_HIGHADDR" TYPE="std_logic_vector" VALUE="0x804131FF"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="mbref_mio_0_IP2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xps_intc_0" PORT="Intr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHzMMCM0" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHzMMCM0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="SPLB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_UABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_PAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_SAValid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPrim"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_masterID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_abort"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_busLock"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_RNW"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="7" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_MSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_size"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_type"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_lockErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="63" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdBurst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendReq"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_wrPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_rdPendPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_reqPri"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="PLB_TAttribute"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_addrAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_SSize"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rearbitrate"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_wrBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="63" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdWdAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdDAck"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdComp"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_rdBTerm"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="3" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MBusy"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="3" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MWrErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="3" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MRdErr"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="3" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mb_plb" PORT="Sl_MIRQ"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2151677952" BASENAME="C_BASEADDR" BASEVALUE="0x80400000" HIGHDECIMAL="2151743487" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8040FFFF" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151743488" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0x80410000" HIGHDECIMAL="2151743999" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0x804101FF" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151747584" BASENAME="C_MEM1_BASEADDR" BASEVALUE="0x80411000" HIGHDECIMAL="2151748095" HIGHNAME="C_MEM1_HIGHADDR" HIGHVALUE="0x804111FF" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151751680" BASENAME="C_MEM2_BASEADDR" BASEVALUE="0x80412000" HIGHDECIMAL="2151752191" HIGHNAME="C_MEM2_HIGHADDR" HIGHVALUE="0x804121FF" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2151755776" BASENAME="C_MEM3_BASEADDR" BASEVALUE="0x80413000" HIGHDECIMAL="2151756287" HIGHNAME="C_MEM3_HIGHADDR" HIGHVALUE="0x804131FF" MEMTYPE="REGISTER" SIZE="512" SIZEABRV="512">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="0"/>
      </INTERRUPTINFO>
    </MODULE>
  </MODULES>

</EDKSYSTEM>