TABLE OF CONTENTS
Overview Block Diagram External Ports Processor microblaze_0 Debuggers mdm_0 Interrupt Controllers xps_intc_0 Busses dlmb ilmb mb_plb Memory lmb_bram Memory Controllers dlmb_cntlr ilmb_cntlr mpmc_0 xps_mch_emc_0 Peripherals xps_ether_0 xps_gpio_0 xps_gpio_1 xps_gpio_2 xps_gpio_3 xps_timer_0 xps_uart_0 IP clock_generator_0 proc_sys_reset_0 Timing Information

Overview | TOC
--- | ---

Resources Used
1 | MicroBlaze
1 | Processor Local Bus (PLB) 4.6
2 | Local Memory Bus (LMB) 1.0
1 | Block RAM (BRAM) Block
2 | LMB BRAM Controller
1 | Multi-Port Memory Controller(DDR/DDR2/SDRAM)
1 | XPS Multi-Channel External Memory Controller(SRAM/Flash)
4 | XPS General Purpose IO
1 | XPS Timer/Counter
1 | XPS UART (16550-style)
1 | XPS LocalLink Tri-mode Ethernet MAC
1 | Clock Generator
1 | MicroBlaze Debug Module (MDM)
1 | Processor System Reset Module
1 | XPS Interrupt Controller

Specifics
Generated | Wed Jan 22 11:41:12 2014
EDK Version | 11.4
Device Family | spartan3adsp
Device | xc3sd1800afg676-4

Block Diagram | TOC
--- | ---

External Ports | TOC
--- | ---

These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
SHARED | fpga_0_rst_1_sys_rst_pin | I | 1 | sys_rst_s | RESET
clock_generator_0 | fpga_0_clk_1_sys_clk_pin | I | 1 | dcm_clk_s | CLK
mpmc_0 | fpga_0_mpmc_0_DDR2_DQS_Div_I_pin | I | 1 | fpga_0_mpmc_0_DDR2_DQS_Div_I_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_DQS_n_pin | IO | 3:0 | fpga_0_mpmc_0_DDR2_DQS_n_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_DQS_pin | IO | 3:0 | fpga_0_mpmc_0_DDR2_DQS_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_DQ_pin | IO | 31:0 | fpga_0_mpmc_0_DDR2_DQ_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_Addr_pin | O | 12:0 | fpga_0_mpmc_0_DDR2_Addr_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_BankAddr_pin | O | 1:0 | fpga_0_mpmc_0_DDR2_BankAddr_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_CAS_n_pin | O | 1 | fpga_0_mpmc_0_DDR2_CAS_n_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_CE_pin | O | 1 | fpga_0_mpmc_0_DDR2_CE_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_CS_n_pin | O | 1 | fpga_0_mpmc_0_DDR2_CS_n_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_Clk_n_pin | O | 1:0 | fpga_0_mpmc_0_DDR2_Clk_n_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_Clk_pin | O | 1:0 | fpga_0_mpmc_0_DDR2_Clk_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_DM_pin | O | 3:0 | fpga_0_mpmc_0_DDR2_DM_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_DQS_Div_O_pin | O | 1 | fpga_0_mpmc_0_DDR2_DQS_Div_O_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_ODT_pin | O | 1 | fpga_0_mpmc_0_DDR2_ODT_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_RAS_n_pin | O | 1 | fpga_0_mpmc_0_DDR2_RAS_n_pin |
mpmc_0 | fpga_0_mpmc_0_DDR2_WE_n_pin | O | 1 | fpga_0_mpmc_0_DDR2_WE_n_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_RXD_0_pin | I | 7:0 | fpga_0_xps_ether_0_GMII_RXD_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_RX_CLK_0_pin | I | 1 | fpga_0_xps_ether_0_GMII_RX_CLK_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_RX_DV_0_pin | I | 1 | fpga_0_xps_ether_0_GMII_RX_DV_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_RX_ER_0_pin | I | 1 | fpga_0_xps_ether_0_GMII_RX_ER_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_MII_TX_CLK_0_pin | I | 1 | fpga_0_xps_ether_0_MII_TX_CLK_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_MDIO_0_pin | IO | 1 | fpga_0_xps_ether_0_MDIO_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_TXD_0_pin | O | 7:0 | fpga_0_xps_ether_0_GMII_TXD_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_TX_CLK_0_pin | O | 1 | fpga_0_xps_ether_0_GMII_TX_CLK_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_TX_EN_0_pin | O | 1 | fpga_0_xps_ether_0_GMII_TX_EN_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_GMII_TX_ER_0_pin | O | 1 | fpga_0_xps_ether_0_GMII_TX_ER_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_MDC_0_pin | O | 1 | fpga_0_xps_ether_0_MDC_0_pin |
xps_ether_0 | fpga_0_xps_ether_0_TemacPhy_RST_n_pin | O | 1 | fpga_0_xps_ether_0_TemacPhy_RST_n_pin |
xps_gpio_1 | fpga_0_xps_gpio_1_GPIO_IO_I_pin | I | 0:3 | fpga_0_xps_gpio_1_GPIO_IO_I_pin |
xps_gpio_2 | fpga_0_xps_gpio_2_GPIO_IO_I_pin | I | 0:7 | fpga_0_xps_gpio_2_GPIO_IO_I_pin |
xps_gpio_3 | fpga_0_xps_gpio_3_GPIO_IO_O_pin | O | 0:7 | fpga_0_xps_gpio_3_GPIO_IO_O_pin |
xps_mch_emc_0 | fpga_0_xps_mch_emc_0_Mem_DQ_pin | IO | 0:7 | fpga_0_xps_mch_emc_0_Mem_DQ_pin |
xps_mch_emc_0 | fpga_0_xps_mch_emc_0_WEN_pin | IO | 1 | fpga_0_xps_mch_emc_0_WEN_pin |
xps_mch_emc_0 | fpga_0_xps_mch_emc_0_Mem_CEN_pin | O | 1 | fpga_0_xps_mch_emc_0_Mem_CEN_pin |
xps_mch_emc_0 | fpga_0_xps_mch_emc_0_Mem_OEN_pin | O | 1 | fpga_0_xps_mch_emc_0_Mem_OEN_pin |
xps_mch_emc_0 | fpga_0_xps_mch_emc_0_Mem_RPN_pin | O | 1 | fpga_0_xps_mch_emc_0_Mem_RPN_pin |
xps_uart_0 | fpga_0_xps_uart_0_sin_pin | I | 1 | fpga_0_xps_uart_0_sin_pin |
xps_uart_0 | fpga_0_xps_uart_0_sout_pin | O | 1 | fpga_0_xps_uart_0_sout_pin |
__NOC__ | fpga_0_xps_mch_emc_0_Mem_A_pin | O | 8:31 | fpga_0_xps_mch_emc_0_Mem_A_pin_vslice_8_31_concat |

Processors | TOC
--- | ---

microblaze_0 MicroBlaze The MicroBlaze 32 bit soft processor

IP Specs
Core | Version | Documentation
--- | --- | ---
microblaze | 7.20.d | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | MB_RESET | I | 1 | mb_reset
1 | INTERRUPT | I | 1 | microblaze_0_Interrupt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
DXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_0_DXCL | mpmc_0
IXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_0_IXCL | mpmc_0
DPLB | MASTER | PLBV46 | mb_plb | xps_gpio_3
IPLB | MASTER | PLBV46 | mb_plb | xps_gpio_3
DLMB | MASTER | LMB | dlmb | dlmb_cntlr
ILMB | MASTER | LMB | ilmb | ilmb_cntlr
DEBUG | TARGET | XIL_MBDEBUG2 | microblaze_0_mdm_bus | mdm_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_INSTANCE | microblaze
C_DCACHE_BASEADDR | 0x20000000
C_DCACHE_HIGHADDR | 0x27FFFFFF
C_ICACHE_BASEADDR | 0x20000000
C_ICACHE_HIGHADDR | 0x27FFFFFF
C_ADDR_TAG_BITS | 17
C_ALLOW_DCACHE_WR | 1
C_ALLOW_ICACHE_WR | 1
C_AREA_OPTIMIZED | 0
C_CACHE_BYTE_SIZE | 16384
C_DATA_SIZE | 32
C_DCACHE_ADDR_TAG | 17
C_DCACHE_ALWAYS_USED | 1
C_DCACHE_BYTE_SIZE | 16384
C_DCACHE_INTERFACE | 0
C_DCACHE_LINE_LEN | 4
C_DCACHE_USE_FSL | 1
C_DCACHE_USE_WRITEBACK | 0
C_DEBUG_ENABLED | 1
C_DIV_ZERO_EXCEPTION | 1
C_DOPB_BUS_EXCEPTION | 0
C_DPLB_BURST_EN | 0
C_DPLB_BUS_EXCEPTION | 1
C_DPLB_DWIDTH | 32
C_DPLB_NATIVE_DWIDTH | 32
C_DPLB_P2P | 0
C_DYNAMIC_BUS_SIZING | 1
C_D_LMB | 1
C_D_OPB | 1
C_D_PLB | 0
C_EDGE_IS_POSITIVE | 1
C_FPU_EXCEPTION | 1
C_FSL_DATA_SIZE | 32
C_FSL_EXCEPTION | 0
C_FSL_LINKS | 0
C_ICACHE_ALWAYS_USED | 1
C_ICACHE_INTERFACE | 0
C_ICACHE_LINE_LEN | 8
C_ICACHE_USE_FSL | 1

Name | Value
C_ILL_OPCODE_EXCEPTION | 1
C_INTERCONNECT | 1
C_INTERRUPT_IS_EDGE | 0
C_IOPB_BUS_EXCEPTION | 0
C_IPLB_BURST_EN | 0
C_IPLB_BUS_EXCEPTION | 1
C_IPLB_DWIDTH | 32
C_IPLB_NATIVE_DWIDTH | 32
C_IPLB_P2P | 0
C_I_LMB | 1
C_I_OPB | 1
C_I_PLB | 0
C_MMU_DTLB_SIZE | 4
C_MMU_ITLB_SIZE | 2
C_MMU_TLB_ACCESS | 3
C_MMU_ZONES | 2
C_NUMBER_OF_PC_BRK | 1
C_NUMBER_OF_RD_ADDR_BRK | 0
C_NUMBER_OF_WR_ADDR_BRK | 0
C_OPCODE_0x0_ILLEGAL | 1
C_PVR | 2
C_PVR_USER1 | 0x00
C_PVR_USER2 | 0x00000000
C_RESET_MSR | 0x00000000
C_SCO | 0
C_UNALIGNED_EXCEPTIONS | 1
C_USE_BARREL | 1
C_USE_DCACHE | 1
C_USE_DIV | 1
C_USE_EXTENDED_FSL_INSTR | 0
C_USE_EXT_BRK | 0
C_USE_EXT_NM_BRK | 0
C_USE_FPU | 1
C_USE_HW_MUL | 1
C_USE_ICACHE | 1
C_USE_INTERRUPT | 0
C_USE_MMU | 3
C_USE_MSR_INSTR | 1
C_USE_PCMP_INSTR | 1

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Debuggers | TOC
--- | ---

mdm_0 MicroBlaze Debug Module (MDM) Debug module for MicroBlaze Soft Processor.

IP Specs
Core | Version | Documentation
--- | --- | ---
mdm | 1.00.g | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | Debug_SYS_Rst | O | 1 | Debug_SYS_Rst
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
MBDEBUG_0 | INITIATOR | XIL_MBDEBUG2 | microblaze_0_mdm_bus | microblaze_0
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x8FFF0000
C_HIGHADDR | 0x8FFFFFFF
C_INTERCONNECT | 1
C_JTAG_CHAIN | 2
C_MB_DBG_PORTS | 1
C_OPB_AWIDTH | 32
C_OPB_DWIDTH | 32
C_SPLB_AWIDTH | 32

Name | Value
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 3
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 8
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0
C_UART_WIDTH | 8
C_USE_UART | 1
C_WRITE_FSL_PORTS | 0

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Interrupt Controllers | TOC
--- | ---

xps_intc_0 XPS Interrupt Controller intc core attached to the PLBV46

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_intc | 2.00.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | Intr | I | 1 | xps_uart_0_IP2INTC_Irpt&xps_ether_0_TemacIntc0_Irpt&mpmc_0_SDMA1_Tx_IntOut&mpmc_0_SDMA1_Rx_IntOut&xps_timer_0_Interrupt
1 | Irq | O | 1 | microblaze_0_Interrupt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0
Interrupt Priorities
PRIORITY | SIGNAL | INSTANCE
0 | xps_uart_0_IP2INTC_Irpt | xps_uart_0
1 | xps_ether_0_TemacIntc0_Irpt | xps_ether_0
2 | mpmc_0_SDMA1_Tx_IntOut | mpmc_0
3 | mpmc_0_SDMA1_Rx_IntOut | mpmc_0
4 | xps_timer_0_Interrupt | xps_timer_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x8AFF0000
C_HIGHADDR | 0x8AFFFFFF
C_HAS_CIE | 1
C_HAS_IPR | 1
C_HAS_IVR | 1
C_HAS_SIE | 1
C_IRQ_ACTIVE | 1
C_IRQ_IS_LEVEL | 1
C_KIND_OF_EDGE | 0xFFFFFFFF

Name | Value
C_KIND_OF_INTR | 0xFFFFFFFF
C_KIND_OF_LVL | 0xFFFFFFFF
C_NUM_INTR_INPUTS | 2
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 1
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 1
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Busses | TOC
--- | ---

dlmb Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core | Version | Documentation
--- | --- | ---
lmb_v10 | 1.00.a | IP

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | LMB_Clk | I | 1 | clk_62_5000MHz
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | DLMB
dlmb_cntlr | SLAVE | SLMB

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_LMB_NUM_SLAVES | 4

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

ilmb Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core | Version | Documentation
--- | --- | ---
lmb_v10 | 1.00.a | IP

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | LMB_Clk | I | 1 | clk_62_5000MHz
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | ILMB
ilmb_cntlr | SLAVE | SLMB

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_LMB_NUM_SLAVES | 4

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

mb_plb Processor Local Bus (PLB) 4.6 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core | Version | Documentation
--- | --- | ---
plb_v46 | 1.04.a | IP

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | PLB_Clk | I | 1 | clk_62_5000MHz
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | DPLB
microblaze_0 | MASTER | IPLB
xps_gpio_3 | SLAVE | SPLB
xps_gpio_1 | SLAVE | SPLB
xps_gpio_2 | SLAVE | SPLB
mpmc_0 | SLAVE | SDMA_CTRL1
xps_timer_0 | SLAVE | SPLB
xps_uart_0 | SLAVE | SPLB
xps_mch_emc_0 | SLAVE | SPLB
xps_ether_0 | SLAVE | SPLB
mdm_0 | SLAVE | SPLB
xps_intc_0 | SLAVE | SPLB
xps_gpio_0 | SLAVE | SPLB

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0b1111111111
C_HIGHADDR | 0b0000000000
C_ADDR_PIPELINING_TYPE | 1
C_ARB_TYPE | 0
C_DCR_AWIDTH | 10
C_DCR_DWIDTH | 32
C_DCR_INTFCE | 0
C_EXT_RESET_HIGH | 1

Name | Value
C_IRQ_ACTIVE | 1
C_NUM_CLK_PLB2OPB_REARB | 5
C_P2P | 0
C_PLBV46_AWIDTH | 32
C_PLBV46_DWIDTH | 64
C_PLBV46_MID_WIDTH | 2
C_PLBV46_NUM_MASTERS | 4
C_PLBV46_NUM_SLAVES | 8

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Memorys | TOC
--- | ---

lmb_bram Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core | Version | Documentation
--- | --- | ---
bram_block | 1.00.a | IP

Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
--- | --- | --- | --- | ---
PORTA | TARGET | XIL_BRAM | ilmb_port | ilmb_cntlr
PORTB | TARGET | XIL_BRAM | dlmb_port | dlmb_cntlr

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex2
C_MEMSIZE | 2048
C_NUM_WE | 4
C_PORT_AWIDTH | 32
C_PORT_DWIDTH | 32

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Memory Controllers | TOC
--- | ---

dlmb_cntlr LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core | Version | Documentation
--- | --- | ---
lmb_bram_if_cntlr | 2.10.b | IP | DRIVER

Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
--- | --- | --- | --- | ---
BRAM_PORT | INITIATOR | XIL_BRAM | dlmb_port | lmb_bram
SLMB | SLAVE | LMB | dlmb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x00001FFF
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_MASK | 0x00800000

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

ilmb_cntlr LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core | Version | Documentation
--- | --- | ---
lmb_bram_if_cntlr | 2.10.b | IP | DRIVER

Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
--- | --- | --- | --- | ---
BRAM_PORT | INITIATOR | XIL_BRAM | ilmb_port | lmb_bram
SLMB | SLAVE | LMB | ilmb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x00001FFF
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_MASK | 0x00800000

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

mpmc_0 Multi-Port Memory Controller(DDR/DDR2/SDRAM) Multi-port memory controller.

IP Specs
Core | Version | Documentation
--- | --- | ---
mpmc | 5.04.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | SDMA1_Clk | I | 1 | clk_62_5000MHz
1 | SDMA1_Rx_IntOut | O | 1 | mpmc_0_SDMA1_Rx_IntOut
2 | SDMA1_Tx_IntOut | O | 1 | mpmc_0_SDMA1_Tx_IntOut
3 | MPMC_Clk0 | I | 1 | clk_125_0000MHzDCM0
4 | MPMC_Clk90 | I | 1 | clk_125_0000MHz90DCM0
5 | MPMC_Rst | I | 1 | sys_periph_reset
6 | DDR2_Clk | O | 1 | fpga_0_mpmc_0_DDR2_Clk_pin
7 | DDR2_Clk_n | O | 1 | fpga_0_mpmc_0_DDR2_Clk_n_pin
8 | DDR2_CE | O | 1 | fpga_0_mpmc_0_DDR2_CE_pin
9 | DDR2_CS_n | O | 1 | fpga_0_mpmc_0_DDR2_CS_n_pin
10 | DDR2_ODT | O | 1 | fpga_0_mpmc_0_DDR2_ODT_pin
11 | DDR2_RAS_n | O | 1 | fpga_0_mpmc_0_DDR2_RAS_n_pin
12 | DDR2_CAS_n | O | 1 | fpga_0_mpmc_0_DDR2_CAS_n_pin
13 | DDR2_WE_n | O | 1 | fpga_0_mpmc_0_DDR2_WE_n_pin
14 | DDR2_BankAddr | O | 1 | fpga_0_mpmc_0_DDR2_BankAddr_pin
15 | DDR2_Addr | O | 1 | fpga_0_mpmc_0_DDR2_Addr_pin
16 | DDR2_DQ | IO | 1 | fpga_0_mpmc_0_DDR2_DQ_pin
17 | DDR2_DM | O | 1 | fpga_0_mpmc_0_DDR2_DM_pin
18 | DDR2_DQS | IO | 1 | fpga_0_mpmc_0_DDR2_DQS_pin
19 | DDR2_DQS_n | IO | 1 | fpga_0_mpmc_0_DDR2_DQS_n_pin
20 | DDR2_DQS_Div_O | O | 1 | fpga_0_mpmc_0_DDR2_DQS_Div_O_pin
21 | DDR2_DQS_Div_I | I | 1 | fpga_0_mpmc_0_DDR2_DQS_Div_I_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SDMA_CTRL1 | SLAVE | PLBV46 | mb_plb | microblaze_0
XCL0 | TARGET | XIL_MEMORY_CHANNEL | microblaze_0_IXCL | microblaze_0
XCL0_B | TARGET | XIL_MEMORY_CHANNEL | microblaze_0_DXCL | microblaze_0
SDMA_LL1 | TARGET | XIL_LL_DMA | xps_ether_0_LLINK0 | xps_ether_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_MPMC_BASEADDR | 0x20000000
C_MPMC_CTRL_BASEADDR | 0xFFFFFFFF
C_MPMC_CTRL_HIGHADDR | 0x00000000
C_MPMC_HIGHADDR | 0x27FFFFFF
C_MPMC_SW_BASEADDR | 0xFFFFFFFF
C_MPMC_SW_HIGHADDR | 0x00000000
C_PIM0_BASEADDR | 0xFFFFFFFF
C_PIM0_HIGHADDR | 0x00000000
C_PIM1_BASEADDR | 0xFFFFFFFF
C_PIM1_HIGHADDR | 0x00000000
C_PIM2_BASEADDR | 0xFFFFFFFF
C_PIM2_HIGHADDR | 0x00000000
C_PIM3_BASEADDR | 0xFFFFFFFF
C_PIM3_HIGHADDR | 0x00000000
C_PIM4_BASEADDR | 0xFFFFFFFF
C_PIM4_HIGHADDR | 0x00000000
C_PIM5_BASEADDR | 0xFFFFFFFF
C_PIM5_HIGHADDR | 0x00000000
C_PIM6_BASEADDR | 0xFFFFFFFF
C_PIM6_HIGHADDR | 0x00000000
C_PIM7_BASEADDR | 0xFFFFFFFF
C_PIM7_HIGHADDR | 0x00000000
C_SDMA_CTRL0_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL0_HIGHADDR | 0x00000000
C_SDMA_CTRL1_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL1_HIGHADDR | 0x00000000
C_SDMA_CTRL2_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL2_HIGHADDR | 0x00000000
C_SDMA_CTRL3_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL3_HIGHADDR | 0x00000000
C_SDMA_CTRL4_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL4_HIGHADDR | 0x00000000
C_SDMA_CTRL5_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL5_HIGHADDR | 0x00000000
C_SDMA_CTRL6_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL6_HIGHADDR | 0x00000000
C_SDMA_CTRL7_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL7_HIGHADDR | 0x00000000
C_SDMA_CTRL_BASEADDR | 0x8ADF0000
C_SDMA_CTRL_HIGHADDR | 0x8ADFFFFF
C_ALL_PIMS_SHARE_ADDRESSES | 1
C_ARB0_ALGO | ROUND_ROBIN
C_ARB0_NUM_SLOTS | 8
C_ARB0_SLOT0 | 01234567
C_ARB0_SLOT1 | 12345670
C_ARB0_SLOT10 | 23456701
C_ARB0_SLOT11 | 34567012
C_ARB0_SLOT12 | 45670123
C_ARB0_SLOT13 | 56701234
C_ARB0_SLOT14 | 67012345
C_ARB0_SLOT15 | 70123456
C_ARB0_SLOT2 | 23456701
C_ARB0_SLOT3 | 34567012
C_ARB0_SLOT4 | 45670123
C_ARB0_SLOT5 | 56701234
C_ARB0_SLOT6 | 67012345
C_ARB0_SLOT7 | 70123456
C_ARB0_SLOT8 | 01234567
C_ARB0_SLOT9 | 12345670
C_ARB_BRAM_INIT_00 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_01 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_02 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_03 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_04 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_05 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_06 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_07 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_PIPELINE | 1
C_ARB_USE_DEFAULT | 0
C_B16_REPEAT_CNT | 0
C_B32_REPEAT_CNT | 0
C_B64_REPEAT_CNT | 0
C_BASEADDR_CTRL0 | 0x000
C_BASEADDR_CTRL1 | 0x00E
C_BASEADDR_CTRL10 | 0x09E
C_BASEADDR_CTRL11 | 0x0A6
C_BASEADDR_CTRL12 | 0x0AE
C_BASEADDR_CTRL13 | 0x0B6
C_BASEADDR_CTRL14 | 0x0BE
C_BASEADDR_CTRL15 | 0x0D1
C_BASEADDR_CTRL2 | 0x018
C_BASEADDR_CTRL3 | 0x026
C_BASEADDR_CTRL4 | 0x030
C_BASEADDR_CTRL5 | 0x03E
C_BASEADDR_CTRL6 | 0x048
C_BASEADDR_CTRL7 | 0x05C
C_BASEADDR_CTRL8 | 0x06B
C_BASEADDR_CTRL9 | 0x087
C_CTRL_AP_COL_CNT_ENABLE_INDEX | 0
C_CTRL_AP_COL_CNT_LOAD_INDEX | 0
C_CTRL_AP_COL_DELAY | 0
C_CTRL_AP_OTF_ADDR12_INDEX | 0
C_CTRL_AP_PIPELINE1_CE_DELAY | 0
C_CTRL_AP_PI_ADDR_CE_DELAY | 0
C_CTRL_AP_PORT_SELECT_DELAY | 0
C_CTRL_AP_PRECHARGE_ADDR10_INDEX | 0
C_CTRL_AP_ROW_COL_SEL_INDEX | 0
C_CTRL_ARB_RDMODWR_DELAY | 0
C_CTRL_BRAM_INITP_00 | 0x1111111111110001111110111111111111111001111110111111111111111001
C_CTRL_BRAM_INITP_01 | 0x1110000000000000000011111111111111111111111111000000000111111011
C_CTRL_BRAM_INITP_02 | 0x1110000000000000000000000000000000011111111111111111111111111111
C_CTRL_BRAM_INITP_03 | 0x0000000000000000000000000000000000000000000000001111111111111111
C_CTRL_BRAM_INITP_04 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_05 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_06 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_07 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INIT_00 | 0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_01 | 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_02 | 0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC
C_CTRL_BRAM_INIT_03 | 0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_04 | 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_05 | 0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC
C_CTRL_BRAM_INIT_06 | 0x000002FC000002FC000002FC0000093C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_07 | 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_08 | 0x000002FC000002FC000002FC000042E8000002FC000006FD000016F4000082FC
C_CTRL_BRAM_INIT_09 | 0x000029240000093C000029240000093C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_0A | 0x000002FC000002FD000002FC000002FC000002FC0000093C000029240000093C
C_CTRL_BRAM_INIT_0B | 0x000016F4000082FC000082FC000082F8000002FC000002FC000002FC000042E8
C_CTRL_BRAM_INIT_0C | 0x000042E8000006FC000026F5000006FC000026F4000006FC000026F4000006FC
C_CTRL_BRAM_INIT_0D | 0x0000093C000019240000803C000082FC000082F8000002FC000002FC000002FC
C_CTRL_BRAM_INIT_0E | 0x0000093C000029240000093C000029240000093C000029240000093C00002924
C_CTRL_BRAM_INIT_0F | 0x000002FC000002FC0000093C000029240000093C000029240000093C00002924
C_CTRL_BRAM_INIT_10 | 0x000082F8000002FC000002FC000002FC000042E8000002FC000002FD000002FC
C_CTRL_BRAM_INIT_11 | 0x000006FC000026F4000006FC000026F4000006FC000016F4000082FC000082FC
C_CTRL_BRAM_INIT_12 | 0x000006FC000026F4000006FC000026F4000006FC000026F4000006FC000026F4
C_CTRL_BRAM_INIT_13 | 0x000002FC000002FC000002FC000002FC000002FC000042E8000006FC000026F5
C_CTRL_BRAM_INIT_14 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_15 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_16 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_17 | 0x000002FC000042E8000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_18 | 0x000002FC000002FC000002FC000002FC000002FC000002F0000002FC000002FC
C_CTRL_BRAM_INIT_19 | 0x000002FC000002FC000002FC000002FC000002FD000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1A | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1B | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1C | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1D | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1E | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1F | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_20 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_21 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_22 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_23 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_24 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_25 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_26 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_27 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_28 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_29 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2A | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2B | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2C | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2D | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2E | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2F | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_30 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_31 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_32 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_33 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_34 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_35 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_36 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_37 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_38 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_39 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3A | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3B | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3C | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3D | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3E | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3F | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_SRVAL | 0x0000002FC
C_CTRL_COMPLETE_INDEX | 0
C_CTRL_DFI_CAS_N_0_INDEX | 0
C_CTRL_DFI_CAS_N_1_INDEX | 0
C_CTRL_DFI_RAS_N_0_INDEX | 0
C_CTRL_DFI_RAS_N_1_INDEX | 0
C_CTRL_DFI_RDDATA_EN_INDEX | 0
C_CTRL_DFI_WE_N_0_INDEX | 0
C_CTRL_DFI_WE_N_1_INDEX | 0
C_CTRL_DFI_WRDATA_EN_INDEX | 0
C_CTRL_DP_LOAD_RDWDADDR_DELAY | 0
C_CTRL_DP_RDFIFO_PUSH_INDEX | 0
C_CTRL_DP_RDFIFO_WHICHPORT_DELAY | 0
C_CTRL_DP_SIZE_DELAY | 0
C_CTRL_DP_WRFIFO_POP_INDEX | 0
C_CTRL_DP_WRFIFO_WHICHPORT_DELAY | 0
C_CTRL_IS_WRITE_INDEX | 0
C_CTRL_PHYIF_CAS_N_INDEX | 0
C_CTRL_PHYIF_DQS_O_INDEX | 0
C_CTRL_PHYIF_DUMMYREADSTART_DELAY | 0
C_CTRL_PHYIF_FORCE_DM_INDEX | 0
C_CTRL_PHYIF_RAS_N_INDEX | 0
C_CTRL_PHYIF_WE_N_INDEX | 0
C_CTRL_Q0_DELAY | 0
C_CTRL_Q10_DELAY | 0
C_CTRL_Q11_DELAY | 0
C_CTRL_Q12_DELAY | 0
C_CTRL_Q13_DELAY | 0
C_CTRL_Q14_DELAY | 0
C_CTRL_Q15_DELAY | 0
C_CTRL_Q16_DELAY | 0
C_CTRL_Q17_DELAY | 0
C_CTRL_Q18_DELAY | 0
C_CTRL_Q19_DELAY | 0
C_CTRL_Q1_DELAY | 0
C_CTRL_Q20_DELAY | 0
C_CTRL_Q21_DELAY | 0
C_CTRL_Q22_DELAY | 0
C_CTRL_Q23_DELAY | 0
C_CTRL_Q24_DELAY | 0
C_CTRL_Q25_DELAY | 0
C_CTRL_Q26_DELAY | 0
C_CTRL_Q27_DELAY | 0
C_CTRL_Q28_DELAY | 0
C_CTRL_Q29_DELAY | 0
C_CTRL_Q2_DELAY | 0
C_CTRL_Q30_DELAY | 0
C_CTRL_Q31_DELAY | 0
C_CTRL_Q32_DELAY | 0
C_CTRL_Q33_DELAY | 0
C_CTRL_Q34_DELAY | 0
C_CTRL_Q35_DELAY | 0
C_CTRL_Q3_DELAY | 0
C_CTRL_Q4_DELAY | 0
C_CTRL_Q5_DELAY | 0
C_CTRL_Q6_DELAY | 0
C_CTRL_Q7_DELAY | 0
C_CTRL_Q8_DELAY | 0
C_CTRL_Q9_DELAY | 0
C_CTRL_REPEAT4_INDEX | 0
C_CTRL_RMW_INDEX | 0
C_CTRL_SKIP_0_INDEX | 0
C_CTRL_SKIP_1_INDEX | 0
C_CTRL_SKIP_2_INDEX | 0
C_DDR2_DQSN_ENABLE | 1
C_DEBUG_REG_ENABLE | 0
C_DEVICE | 5vlx50t
C_ECC_DATA_WIDTH | 0
C_ECC_DEC_THRESHOLD | 1
C_ECC_DEFAULT_ON | 1
C_ECC_DM_WIDTH | 0
C_ECC_DQS_WIDTH | 0
C_ECC_PEC_THRESHOLD | 1
C_ECC_SEC_THRESHOLD | 1
C_HIGHADDR_CTRL0 | 0x00D
C_HIGHADDR_CTRL1 | 0x017
C_HIGHADDR_CTRL10 | 0x0A5
C_HIGHADDR_CTRL11 | 0x0AD
C_HIGHADDR_CTRL12 | 0x0B5
C_HIGHADDR_CTRL13 | 0x0BD
C_HIGHADDR_CTRL14 | 0x0D0
C_HIGHADDR_CTRL15 | 0x0D8
C_HIGHADDR_CTRL2 | 0x025
C_HIGHADDR_CTRL3 | 0x02F
C_HIGHADDR_CTRL4 | 0x03D
C_HIGHADDR_CTRL5 | 0x047
C_HIGHADDR_CTRL6 | 0x05B
C_HIGHADDR_CTRL7 | 0x06A
C_HIGHADDR_CTRL8 | 0x086
C_HIGHADDR_CTRL9 | 0x09D
C_IDELAYCTRL_LOC | NOT_SET
C_IDELAY_CLK_FREQ | DEFAULT
C_INCLUDE_ECC_SUPPORT | 0
C_INCLUDE_ECC_TEST | 0
C_IODELAY_GRP | NOT_SET
C_MAX_REQ_ALLOWED | 1
C_MCB_DQ0_TAP_DELAY_VAL | 0
C_MCB_DQ10_TAP_DELAY_VAL | 0
C_MCB_DQ11_TAP_DELAY_VAL | 0
C_MCB_DQ12_TAP_DELAY_VAL | 0
C_MCB_DQ13_TAP_DELAY_VAL | 0
C_MCB_DQ14_TAP_DELAY_VAL | 0
C_MCB_DQ15_TAP_DELAY_VAL | 0
C_MCB_DQ1_TAP_DELAY_VAL | 0
C_MCB_DQ2_TAP_DELAY_VAL | 0
C_MCB_DQ3_TAP_DELAY_VAL | 0
C_MCB_DQ4_TAP_DELAY_VAL | 0
C_MCB_DQ5_TAP_DELAY_VAL | 0
C_MCB_DQ6_TAP_DELAY_VAL | 0
C_MCB_DQ7_TAP_DELAY_VAL | 0
C_MCB_DQ8_TAP_DELAY_VAL | 0
C_MCB_DQ9_TAP_DELAY_VAL | 0
C_MCB_LDQSN_TAP_DELAY_VAL | 0
C_MCB_LDQSP_TAP_DELAY_VAL | 0
C_MCB_LOC | NOT_SET
C_MCB_UDQSN_TAP_DELAY_VAL | 0
C_MCB_UDQSP_TAP_DELAY_VAL | 0
C_MCB_USE_EXTERNAL_BUFPLL | 0
C_MEM_ADDR_ORDER | BANK_ROW_COLUMN
C_MEM_ADDR_WIDTH | 13
C_MEM_AUTO_SR | ENABLED
C_MEM_BANKADDR_WIDTH | 2
C_MEM_BITS_DATA_PER_DQS | 8
C_MEM_CALIBRATION_BYPASS | NO
C_MEM_CALIBRATION_DELAY | HALF
C_MEM_CALIBRATION_MODE | 1
C_MEM_CALIBRATION_SOFT_IP | FALSE
C_MEM_CAL_WIDTH | DEFAULT
C_MEM_CAS_LATENCY | 3
C_MEM_CAS_WR_LATENCY | 5
C_MEM_CE_WIDTH | 1
C_MEM_CHECK_MAX_INDELAY | 0
C_MEM_CHECK_MAX_TAP_REG | 0
C_MEM_CLK_WIDTH | 2
C_MEM_CS_N_WIDTH | 1
C_MEM_DATA_WIDTH | 32
C_MEM_DM_WIDTH | 4
C_MEM_DQS_IO_COL | 0x000000000000000000
C_MEM_DQS_LOC_COL0 | 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL1 | 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL2 | 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL3 | 0x000000000000000000000000000000000000
C_MEM_DQS_WIDTH | 4
C_MEM_DQ_IO_MS | 0x000000000000000000
C_MEM_DYNAMIC_WRITE_ODT | OFF
C_MEM_HIGH_TEMP_SR | NORMAL
C_MEM_IBUF_LPWR_MODE | DEFAULT
C_MEM_INCDEC_THRESHOLD | 0x02
C_MEM_IODELAY_HP_MODE | DEFAULT
C_MEM_NDQS_COL0 | 0
C_MEM_NDQS_COL1 | 0
C_MEM_NDQS_COL2 | 0
C_MEM_NDQS_COL3 | 0
C_MEM_NUM_DIMMS | 1
C_MEM_NUM_RANKS | 1
C_MEM_OCB_MONITOR | DEFAULT
C_MEM_ODT_TYPE | 0
C_MEM_ODT_WIDTH | 1
C_MEM_PARTNO | MT47H32M16-5E
C_MEM_PART_CAS_A | 0
C_MEM_PART_CAS_A_FMAX | 0
C_MEM_PART_CAS_B | 0
C_MEM_PART_CAS_B_FMAX | 0
C_MEM_PART_CAS_C | 0
C_MEM_PART_CAS_C_FMAX | 0
C_MEM_PART_CAS_D | 0
C_MEM_PART_CAS_D_FMAX | 0
C_MEM_PART_DATA_DEPTH | 16
C_MEM_PART_DATA_WIDTH | 8
C_MEM_PART_NUM_BANK_BITS | 2
C_MEM_PART_NUM_COL_BITS | 9
C_MEM_PART_NUM_ROW_BITS | 13
C_MEM_PART_TAL | 0
C_MEM_PART_TCCD | 0
C_MEM_PART_TDQSS | 1
C_MEM_PART_TMRD | 4
C_MEM_PART_TRAS | 0
C_MEM_PART_TRASMAX | 0
C_MEM_PART_TRC | 0
C_MEM_PART_TRCD | 0
C_MEM_PART_TREFI | 0
C_MEM_PART_TRFC | 0
C_MEM_PART_TRP | 0
C_MEM_PART_TRRD | 0
C_MEM_PART_TRTP | 7500
C_MEM_PART_TWR | 0
C_MEM_PART_TWTR | 0
C_MEM_PART_TZQCS | 64
C_MEM_PART_TZQINIT | 512
C_MEM_PA_SR | 0
C_MEM_PHASE_DETECT | DEFAULT
C_MEM_REDUCED_DRV | 0
C_MEM_REG_DIMM | 0
C_MEM_SIM_CAL_OPTION | DEFAULT
C_MEM_SIM_INIT_OPTION | DEFAULT
C_MEM_SKIP_DYNAMIC_CAL | 1
C_MEM_SKIP_DYN_IN_TERM | 1
C_MEM_SKIP_IN_TERM_CAL | 1
C_MEM_TYPE | DDR2
C_MEM_TZQINIT_MAXCNT | 512
C_MEM_WRLVL | 1
C_MMCM_EXT_LOC | NOT_SET
C_MMCM_INT_LOC | NOT_SET
C_MPMC_CLK0_PERIOD_PS | 1
C_MPMC_CLK_MEM_2X_PERIOD_PS | 1250
C_MPMC_CLK_MEM_PERIOD_PS | 1
C_MPMC_CLK_WR_I0_PHASE | 0
C_MPMC_CLK_WR_I1_PHASE | 0
C_MPMC_CLK_WR_O0_PHASE | 0
C_MPMC_CLK_WR_O1_PHASE | 0
C_MPMC_CTRL_AWIDTH | 32
C_MPMC_CTRL_DWIDTH | 64
C_MPMC_CTRL_MID_WIDTH | 1
C_MPMC_CTRL_NATIVE_DWIDTH | 32
C_MPMC_CTRL_NUM_MASTERS | 1
C_MPMC_CTRL_P2P | 1
C_MPMC_CTRL_SMALLEST_MASTER | 32
C_MPMC_CTRL_SUPPORT_BURSTS | 0
C_NCK_PER_CLK | 1
C_NUM_IDELAYCTRL | 1
C_NUM_PORTS | 2
C_PACKAGE | ff1136
C_PI0_ADDRACK_PIPELINE | 1
C_PI0_PM_DC_CNTR | 1
C_PI0_PM_USED | 1
C_PI0_RD_FIFO_APP_PIPELINE | 1
C_PI0_RD_FIFO_MEM_PIPELINE | 1
C_PI0_RD_FIFO_TYPE | BRAM

Name | Value
C_PI0_WR_FIFO_APP_PIPELINE | 1
C_PI0_WR_FIFO_MEM_PIPELINE | 1
C_PI0_WR_FIFO_TYPE | BRAM
C_PI1_ADDRACK_PIPELINE | 1
C_PI1_PM_DC_CNTR | 1
C_PI1_PM_USED | 1
C_PI1_RD_FIFO_APP_PIPELINE | 1
C_PI1_RD_FIFO_MEM_PIPELINE | 1
C_PI1_RD_FIFO_TYPE | BRAM
C_PI1_WR_FIFO_APP_PIPELINE | 1
C_PI1_WR_FIFO_MEM_PIPELINE | 1
C_PI1_WR_FIFO_TYPE | BRAM
C_PI2_ADDRACK_PIPELINE | 1
C_PI2_PM_DC_CNTR | 1
C_PI2_PM_USED | 1
C_PI2_RD_FIFO_APP_PIPELINE | 1
C_PI2_RD_FIFO_MEM_PIPELINE | 1
C_PI2_RD_FIFO_TYPE | BRAM
C_PI2_WR_FIFO_APP_PIPELINE | 1
C_PI2_WR_FIFO_MEM_PIPELINE | 1
C_PI2_WR_FIFO_TYPE | BRAM
C_PI3_ADDRACK_PIPELINE | 1
C_PI3_PM_DC_CNTR | 1
C_PI3_PM_USED | 1
C_PI3_RD_FIFO_APP_PIPELINE | 1
C_PI3_RD_FIFO_MEM_PIPELINE | 1
C_PI3_RD_FIFO_TYPE | BRAM
C_PI3_WR_FIFO_APP_PIPELINE | 1
C_PI3_WR_FIFO_MEM_PIPELINE | 1
C_PI3_WR_FIFO_TYPE | BRAM
C_PI4_ADDRACK_PIPELINE | 1
C_PI4_PM_DC_CNTR | 1
C_PI4_PM_USED | 1
C_PI4_RD_FIFO_APP_PIPELINE | 1
C_PI4_RD_FIFO_MEM_PIPELINE | 1
C_PI4_RD_FIFO_TYPE | BRAM
C_PI4_WR_FIFO_APP_PIPELINE | 1
C_PI4_WR_FIFO_MEM_PIPELINE | 1
C_PI4_WR_FIFO_TYPE | BRAM
C_PI5_ADDRACK_PIPELINE | 1
C_PI5_PM_DC_CNTR | 1
C_PI5_PM_USED | 1
C_PI5_RD_FIFO_APP_PIPELINE | 1
C_PI5_RD_FIFO_MEM_PIPELINE | 1
C_PI5_RD_FIFO_TYPE | BRAM
C_PI5_WR_FIFO_APP_PIPELINE | 1
C_PI5_WR_FIFO_MEM_PIPELINE | 1
C_PI5_WR_FIFO_TYPE | BRAM
C_PI6_ADDRACK_PIPELINE | 1
C_PI6_PM_DC_CNTR | 1
C_PI6_PM_USED | 1
C_PI6_RD_FIFO_APP_PIPELINE | 1
C_PI6_RD_FIFO_MEM_PIPELINE | 1
C_PI6_RD_FIFO_TYPE | BRAM
C_PI6_WR_FIFO_APP_PIPELINE | 1
C_PI6_WR_FIFO_MEM_PIPELINE | 1
C_PI6_WR_FIFO_TYPE | BRAM
C_PI7_ADDRACK_PIPELINE | 1
C_PI7_PM_DC_CNTR | 1
C_PI7_PM_USED | 1
C_PI7_RD_FIFO_APP_PIPELINE | 1
C_PI7_RD_FIFO_MEM_PIPELINE | 1
C_PI7_RD_FIFO_TYPE | BRAM
C_PI7_WR_FIFO_APP_PIPELINE | 1
C_PI7_WR_FIFO_MEM_PIPELINE | 1
C_PI7_WR_FIFO_TYPE | BRAM
C_PIM0_BASETYPE | 1
C_PIM0_B_SUBTYPE | INACTIVE
C_PIM0_DATA_WIDTH | 64
C_PIM0_OFFSET | 0x00000000
C_PIM0_SUBTYPE | PLB
C_PIM1_BASETYPE | 3
C_PIM1_B_SUBTYPE | INACTIVE
C_PIM1_DATA_WIDTH | 64
C_PIM1_OFFSET | 0x00000000
C_PIM1_SUBTYPE | INACTIVE
C_PIM2_BASETYPE | 0
C_PIM2_B_SUBTYPE | INACTIVE
C_PIM2_DATA_WIDTH | 64
C_PIM2_OFFSET | 0x00000000
C_PIM2_SUBTYPE | INACTIVE
C_PIM3_BASETYPE | 0
C_PIM3_B_SUBTYPE | INACTIVE
C_PIM3_DATA_WIDTH | 64
C_PIM3_OFFSET | 0x00000000
C_PIM3_SUBTYPE | INACTIVE
C_PIM4_BASETYPE | 0
C_PIM4_B_SUBTYPE | INACTIVE
C_PIM4_DATA_WIDTH | 64
C_PIM4_OFFSET | 0x00000000
C_PIM4_SUBTYPE | INACTIVE
C_PIM5_BASETYPE | 0
C_PIM5_B_SUBTYPE | INACTIVE
C_PIM5_DATA_WIDTH | 64
C_PIM5_OFFSET | 0x00000000
C_PIM5_SUBTYPE | INACTIVE
C_PIM6_BASETYPE | 0
C_PIM6_B_SUBTYPE | INACTIVE
C_PIM6_DATA_WIDTH | 64
C_PIM6_OFFSET | 0x00000000
C_PIM6_SUBTYPE | INACTIVE
C_PIM7_BASETYPE | 0
C_PIM7_B_SUBTYPE | INACTIVE
C_PIM7_DATA_WIDTH | 64
C_PIM7_OFFSET | 0x00000000
C_PIM7_SUBTYPE | INACTIVE
C_PM_DC_WIDTH | 48
C_PM_ENABLE | 0
C_PM_GC_CNTR | 1
C_PM_GC_WIDTH | 48
C_PM_SHIFT_CNT_BY | 1
C_PORT_CONFIG | 1
C_PPC440MC0_BURST_LENGTH | 4
C_PPC440MC0_PIPE_STAGES | 1
C_PPC440MC1_BURST_LENGTH | 4
C_PPC440MC1_PIPE_STAGES | 1
C_PPC440MC2_BURST_LENGTH | 4
C_PPC440MC2_PIPE_STAGES | 1
C_PPC440MC3_BURST_LENGTH | 4
C_PPC440MC3_PIPE_STAGES | 1
C_PPC440MC4_BURST_LENGTH | 4
C_PPC440MC4_PIPE_STAGES | 1
C_PPC440MC5_BURST_LENGTH | 4
C_PPC440MC5_PIPE_STAGES | 1
C_PPC440MC6_BURST_LENGTH | 4
C_PPC440MC6_PIPE_STAGES | 1
C_PPC440MC7_BURST_LENGTH | 4
C_PPC440MC7_PIPE_STAGES | 1
C_RD_DATAPATH_TML_MAX_FANOUT | 0
C_SDMA0_COMPLETED_ERR_RX | 1
C_SDMA0_COMPLETED_ERR_TX | 1
C_SDMA0_PI2LL_CLK_RATIO | 1
C_SDMA0_PRESCALAR | 1023
C_SDMA1_COMPLETED_ERR_RX | 1
C_SDMA1_COMPLETED_ERR_TX | 1
C_SDMA1_PI2LL_CLK_RATIO | 2
C_SDMA1_PRESCALAR | 1023
C_SDMA2_COMPLETED_ERR_RX | 1
C_SDMA2_COMPLETED_ERR_TX | 1
C_SDMA2_PI2LL_CLK_RATIO | 1
C_SDMA2_PRESCALAR | 1023
C_SDMA3_COMPLETED_ERR_RX | 1
C_SDMA3_COMPLETED_ERR_TX | 1
C_SDMA3_PI2LL_CLK_RATIO | 1
C_SDMA3_PRESCALAR | 1023
C_SDMA4_COMPLETED_ERR_RX | 1
C_SDMA4_COMPLETED_ERR_TX | 1
C_SDMA4_PI2LL_CLK_RATIO | 1
C_SDMA4_PRESCALAR | 1023
C_SDMA5_COMPLETED_ERR_RX | 1
C_SDMA5_COMPLETED_ERR_TX | 1
C_SDMA5_PI2LL_CLK_RATIO | 1
C_SDMA5_PRESCALAR | 1023
C_SDMA6_COMPLETED_ERR_RX | 1
C_SDMA6_COMPLETED_ERR_TX | 1
C_SDMA6_PI2LL_CLK_RATIO | 1
C_SDMA6_PRESCALAR | 1023
C_SDMA7_COMPLETED_ERR_RX | 1
C_SDMA7_COMPLETED_ERR_TX | 1
C_SDMA7_PI2LL_CLK_RATIO | 1
C_SDMA7_PRESCALAR | 1023
C_SDMA_CTRL0_AWIDTH | 32
C_SDMA_CTRL0_DWIDTH | 64
C_SDMA_CTRL0_MID_WIDTH | 1
C_SDMA_CTRL0_NATIVE_DWIDTH | 32
C_SDMA_CTRL0_NUM_MASTERS | 1
C_SDMA_CTRL0_P2P | 1
C_SDMA_CTRL0_SMALLEST_MASTER | 32
C_SDMA_CTRL0_SUPPORT_BURSTS | 0
C_SDMA_CTRL1_AWIDTH | 32
C_SDMA_CTRL1_DWIDTH | 64
C_SDMA_CTRL1_MID_WIDTH | 1
C_SDMA_CTRL1_NATIVE_DWIDTH | 32
C_SDMA_CTRL1_NUM_MASTERS | 1
C_SDMA_CTRL1_P2P | 1
C_SDMA_CTRL1_SMALLEST_MASTER | 32
C_SDMA_CTRL1_SUPPORT_BURSTS | 0
C_SDMA_CTRL2_AWIDTH | 32
C_SDMA_CTRL2_DWIDTH | 64
C_SDMA_CTRL2_MID_WIDTH | 1
C_SDMA_CTRL2_NATIVE_DWIDTH | 32
C_SDMA_CTRL2_NUM_MASTERS | 1
C_SDMA_CTRL2_P2P | 1
C_SDMA_CTRL2_SMALLEST_MASTER | 32
C_SDMA_CTRL2_SUPPORT_BURSTS | 0
C_SDMA_CTRL3_AWIDTH | 32
C_SDMA_CTRL3_DWIDTH | 64
C_SDMA_CTRL3_MID_WIDTH | 1
C_SDMA_CTRL3_NATIVE_DWIDTH | 32
C_SDMA_CTRL3_NUM_MASTERS | 1
C_SDMA_CTRL3_P2P | 1
C_SDMA_CTRL3_SMALLEST_MASTER | 32
C_SDMA_CTRL3_SUPPORT_BURSTS | 0
C_SDMA_CTRL4_AWIDTH | 32
C_SDMA_CTRL4_DWIDTH | 64
C_SDMA_CTRL4_MID_WIDTH | 1
C_SDMA_CTRL4_NATIVE_DWIDTH | 32
C_SDMA_CTRL4_NUM_MASTERS | 1
C_SDMA_CTRL4_P2P | 1
C_SDMA_CTRL4_SMALLEST_MASTER | 32
C_SDMA_CTRL4_SUPPORT_BURSTS | 0
C_SDMA_CTRL5_AWIDTH | 32
C_SDMA_CTRL5_DWIDTH | 64
C_SDMA_CTRL5_MID_WIDTH | 1
C_SDMA_CTRL5_NATIVE_DWIDTH | 32
C_SDMA_CTRL5_NUM_MASTERS | 1
C_SDMA_CTRL5_P2P | 1
C_SDMA_CTRL5_SMALLEST_MASTER | 32
C_SDMA_CTRL5_SUPPORT_BURSTS | 0
C_SDMA_CTRL6_AWIDTH | 32
C_SDMA_CTRL6_DWIDTH | 64
C_SDMA_CTRL6_MID_WIDTH | 1
C_SDMA_CTRL6_NATIVE_DWIDTH | 32
C_SDMA_CTRL6_NUM_MASTERS | 1
C_SDMA_CTRL6_P2P | 1
C_SDMA_CTRL6_SMALLEST_MASTER | 32
C_SDMA_CTRL6_SUPPORT_BURSTS | 0
C_SDMA_CTRL7_AWIDTH | 32
C_SDMA_CTRL7_DWIDTH | 64
C_SDMA_CTRL7_MID_WIDTH | 1
C_SDMA_CTRL7_NATIVE_DWIDTH | 32
C_SDMA_CTRL7_NUM_MASTERS | 1
C_SDMA_CTRL7_P2P | 1
C_SDMA_CTRL7_SMALLEST_MASTER | 32
C_SDMA_CTRL7_SUPPORT_BURSTS | 0
C_SKIP_1_VALUE | 15
C_SKIP_2_VALUE | 15
C_SKIP_3_VALUE | 15
C_SKIP_4_VALUE | 20
C_SKIP_5_VALUE | 36
C_SKIP_6_VALUE | 20
C_SKIP_7_VALUE | 36
C_SKIP_SIM_INIT_DELAY | 0
C_SPECIAL_BOARD | NONE
C_SPEEDGRADE | -1
C_SPEEDGRADE_INT | 1
C_SPLB0_AWIDTH | 32
C_SPLB0_DWIDTH | 64
C_SPLB0_MID_WIDTH | 1
C_SPLB0_NATIVE_DWIDTH | 64
C_SPLB0_NUM_MASTERS | 1
C_SPLB0_P2P | 1
C_SPLB0_SMALLEST_MASTER | 32
C_SPLB0_SUPPORT_BURSTS | 0
C_SPLB1_AWIDTH | 32
C_SPLB1_DWIDTH | 64
C_SPLB1_MID_WIDTH | 1
C_SPLB1_NATIVE_DWIDTH | 64
C_SPLB1_NUM_MASTERS | 1
C_SPLB1_P2P | 1
C_SPLB1_SMALLEST_MASTER | 32
C_SPLB1_SUPPORT_BURSTS | 0
C_SPLB2_AWIDTH | 32
C_SPLB2_DWIDTH | 64
C_SPLB2_MID_WIDTH | 1
C_SPLB2_NATIVE_DWIDTH | 64
C_SPLB2_NUM_MASTERS | 1
C_SPLB2_P2P | 1
C_SPLB2_SMALLEST_MASTER | 32
C_SPLB2_SUPPORT_BURSTS | 0
C_SPLB3_AWIDTH | 32
C_SPLB3_DWIDTH | 64
C_SPLB3_MID_WIDTH | 1
C_SPLB3_NATIVE_DWIDTH | 64
C_SPLB3_NUM_MASTERS | 1
C_SPLB3_P2P | 1
C_SPLB3_SMALLEST_MASTER | 32
C_SPLB3_SUPPORT_BURSTS | 0
C_SPLB4_AWIDTH | 32
C_SPLB4_DWIDTH | 64
C_SPLB4_MID_WIDTH | 1
C_SPLB4_NATIVE_DWIDTH | 64
C_SPLB4_NUM_MASTERS | 1
C_SPLB4_P2P | 1
C_SPLB4_SMALLEST_MASTER | 32
C_SPLB4_SUPPORT_BURSTS | 0
C_SPLB5_AWIDTH | 32
C_SPLB5_DWIDTH | 64
C_SPLB5_MID_WIDTH | 1
C_SPLB5_NATIVE_DWIDTH | 64
C_SPLB5_NUM_MASTERS | 1
C_SPLB5_P2P | 1
C_SPLB5_SMALLEST_MASTER | 32
C_SPLB5_SUPPORT_BURSTS | 0
C_SPLB6_AWIDTH | 32
C_SPLB6_DWIDTH | 64
C_SPLB6_MID_WIDTH | 1
C_SPLB6_NATIVE_DWIDTH | 64
C_SPLB6_NUM_MASTERS | 1
C_SPLB6_P2P | 1
C_SPLB6_SMALLEST_MASTER | 32
C_SPLB6_SUPPORT_BURSTS | 0
C_SPLB7_AWIDTH | 32
C_SPLB7_DWIDTH | 64
C_SPLB7_MID_WIDTH | 1
C_SPLB7_NATIVE_DWIDTH | 64
C_SPLB7_NUM_MASTERS | 1
C_SPLB7_P2P | 1
C_SPLB7_SMALLEST_MASTER | 32
C_SPLB7_SUPPORT_BURSTS | 0
C_STATIC_PHY_RDDATA_CLK_SEL | 0
C_STATIC_PHY_RDDATA_SWAP_RISE | 0
C_STATIC_PHY_RDEN_DELAY | 5
C_SUBFAMILY | fx
C_TBY4TAPVALUE | 9999
C_TWR | 0
C_USE_MIG_FLOW | 0
C_USE_STATIC_PHY | 0
C_VFBC0_CMD_AFULL_COUNT | 3
C_VFBC0_CMD_FIFO_DEPTH | 32
C_VFBC0_RDWD_DATA_WIDTH | 32
C_VFBC0_RDWD_FIFO_DEPTH | 1024
C_VFBC0_RD_AEMPTY_WD_AFULL_COUNT | 3
C_VFBC1_CMD_AFULL_COUNT | 3
C_VFBC1_CMD_FIFO_DEPTH | 32
C_VFBC1_RDWD_DATA_WIDTH | 32
C_VFBC1_RDWD_FIFO_DEPTH | 1024
C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT | 3
C_VFBC2_CMD_AFULL_COUNT | 3
C_VFBC2_CMD_FIFO_DEPTH | 32
C_VFBC2_RDWD_DATA_WIDTH | 32
C_VFBC2_RDWD_FIFO_DEPTH | 1024
C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT | 3
C_VFBC3_CMD_AFULL_COUNT | 3
C_VFBC3_CMD_FIFO_DEPTH | 32
C_VFBC3_RDWD_DATA_WIDTH | 32
C_VFBC3_RDWD_FIFO_DEPTH | 1024
C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT | 3
C_VFBC4_CMD_AFULL_COUNT | 3
C_VFBC4_CMD_FIFO_DEPTH | 32
C_VFBC4_RDWD_DATA_WIDTH | 32
C_VFBC4_RDWD_FIFO_DEPTH | 1024
C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT | 3
C_VFBC5_CMD_AFULL_COUNT | 3
C_VFBC5_CMD_FIFO_DEPTH | 32
C_VFBC5_RDWD_DATA_WIDTH | 32
C_VFBC5_RDWD_FIFO_DEPTH | 1024
C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT | 3
C_VFBC6_CMD_AFULL_COUNT | 3
C_VFBC6_CMD_FIFO_DEPTH | 32
C_VFBC6_RDWD_DATA_WIDTH | 32
C_VFBC6_RDWD_FIFO_DEPTH | 1024
C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT | 3
C_VFBC7_CMD_AFULL_COUNT | 3
C_VFBC7_CMD_FIFO_DEPTH | 32
C_VFBC7_RDWD_DATA_WIDTH | 32
C_VFBC7_RDWD_FIFO_DEPTH | 1024
C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT | 3
C_WR_DATAPATH_TML_PIPELINE | 1
C_WR_TRAINING_PORT | 0
C_XCL0_B_IN_USE | 1
C_XCL0_B_LINESIZE | 4
C_XCL0_B_WRITEXFER | 1
C_XCL0_LINESIZE | 4
C_XCL0_PIPE_STAGES | 2
C_XCL0_WRITEXFER | 1
C_XCL1_B_IN_USE | 0
C_XCL1_B_LINESIZE | 4
C_XCL1_B_WRITEXFER | 1
C_XCL1_LINESIZE | 4
C_XCL1_PIPE_STAGES | 2
C_XCL1_WRITEXFER | 1
C_XCL2_B_IN_USE | 0
C_XCL2_B_LINESIZE | 4
C_XCL2_B_WRITEXFER | 1
C_XCL2_LINESIZE | 4
C_XCL2_PIPE_STAGES | 2
C_XCL2_WRITEXFER | 1
C_XCL3_B_IN_USE | 0
C_XCL3_B_LINESIZE | 4
C_XCL3_B_WRITEXFER | 1
C_XCL3_LINESIZE | 4
C_XCL3_PIPE_STAGES | 2
C_XCL3_WRITEXFER | 1
C_XCL4_B_IN_USE | 0
C_XCL4_B_LINESIZE | 4
C_XCL4_B_WRITEXFER | 1
C_XCL4_LINESIZE | 4
C_XCL4_PIPE_STAGES | 2
C_XCL4_WRITEXFER | 1
C_XCL5_B_IN_USE | 0
C_XCL5_B_LINESIZE | 4
C_XCL5_B_WRITEXFER | 1
C_XCL5_LINESIZE | 4
C_XCL5_PIPE_STAGES | 2
C_XCL5_WRITEXFER | 1
C_XCL6_B_IN_USE | 0
C_XCL6_B_LINESIZE | 4
C_XCL6_B_WRITEXFER | 1
C_XCL6_LINESIZE | 4
C_XCL6_PIPE_STAGES | 2
C_XCL6_WRITEXFER | 1
C_XCL7_B_IN_USE | 0
C_XCL7_B_LINESIZE | 4
C_XCL7_B_WRITEXFER | 1
C_XCL7_LINESIZE | 4
C_XCL7_PIPE_STAGES | 2
C_XCL7_WRITEXFER | 1

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

xps_mch_emc_0 XPS Multi-Channel External Memory Controller(SRAM/Flash) Xilinx Multi-CHannel (MCH) PLBV46 external memory controller

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_mch_emc | 3.01.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | RdClk | I | 1 | clk_62_5000MHz
1 | Mem_A | O | 1 | 0b00000000 & fpga_0_xps_mch_emc_0_Mem_A_pin_vslice_8_31_concat
2 | Mem_RPN | O | 1 | fpga_0_xps_mch_emc_0_Mem_RPN_pin
3 | Mem_CEN | O | 1 | fpga_0_xps_mch_emc_0_Mem_CEN_pin
4 | Mem_OEN | O | 1 | fpga_0_xps_mch_emc_0_Mem_OEN_pin
5 | Mem_WEN | O | 1 | fpga_0_xps_mch_emc_0_WEN_pin
6 | Mem_DQ | IO | 1 | fpga_0_xps_mch_emc_0_Mem_DQ_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_MEM0_BASEADDR | 0xAF000000
C_MEM0_HIGHADDR | 0xAFFFFFFF
C_MEM1_BASEADDR | 0xFFFFFFFF
C_MEM1_HIGHADDR | 0x00000000
C_MEM2_BASEADDR | 0xFFFFFFFF
C_MEM2_HIGHADDR | 0x00000000
C_MEM3_BASEADDR | 0xFFFFFFFF
C_MEM3_HIGHADDR | 0x00000000
C_INCLUDE_DATAWIDTH_MATCHING_0 | 1
C_INCLUDE_DATAWIDTH_MATCHING_1 | 0
C_INCLUDE_DATAWIDTH_MATCHING_2 | 0
C_INCLUDE_DATAWIDTH_MATCHING_3 | 0
C_INCLUDE_NEGEDGE_IOREGS | 0
C_INCLUDE_PLB_IPIF | 1
C_INCLUDE_WRBUF | 1
C_MAX_MEM_WIDTH | 8
C_MCH0_ACCESSBUF_DEPTH | 16
C_MCH0_PROTOCOL | 0
C_MCH0_RDDATABUF_DEPTH | 16
C_MCH1_ACCESSBUF_DEPTH | 16
C_MCH1_PROTOCOL | 0
C_MCH1_RDDATABUF_DEPTH | 16
C_MCH2_ACCESSBUF_DEPTH | 16
C_MCH2_PROTOCOL | 0
C_MCH2_RDDATABUF_DEPTH | 16
C_MCH3_ACCESSBUF_DEPTH | 16
C_MCH3_PROTOCOL | 0
C_MCH3_RDDATABUF_DEPTH | 16
C_MCH_NATIVE_DWIDTH | 32
C_MCH_SPLB_AWIDTH | 32
C_MCH_SPLB_CLK_PERIOD_PS | 10000
C_MEM0_WIDTH | 8
C_MEM1_WIDTH | 32
C_MEM2_WIDTH | 32
C_MEM3_WIDTH | 32
C_NUM_BANKS_MEM | 1
C_NUM_CHANNELS | 0
C_PAGEMODE_FLASH_0 | 0
C_PAGEMODE_FLASH_1 | 0
C_PAGEMODE_FLASH_2 | 0
C_PAGEMODE_FLASH_3 | 0
C_PRIORITY_MODE | 0
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 1
C_SPLB_NUM_MASTERS | 1
C_SPLB_P2P | 0
C_SPLB_SMALLEST_MASTER | 32

Name | Value
C_SYNCH_MEM_0 | 0
C_SYNCH_MEM_1 | 0
C_SYNCH_MEM_2 | 0
C_SYNCH_MEM_3 | 0
C_SYNCH_PIPEDELAY_0 | 2
C_SYNCH_PIPEDELAY_1 | 2
C_SYNCH_PIPEDELAY_2 | 2
C_SYNCH_PIPEDELAY_3 | 2
C_TAVDV_PS_MEM_0 | 70000
C_TAVDV_PS_MEM_1 | 15000
C_TAVDV_PS_MEM_2 | 15000
C_TAVDV_PS_MEM_3 | 15000
C_TCEDV_PS_MEM_0 | 70000
C_TCEDV_PS_MEM_1 | 15000
C_TCEDV_PS_MEM_2 | 15000
C_TCEDV_PS_MEM_3 | 15000
C_THZCE_PS_MEM_0 | 25000
C_THZCE_PS_MEM_1 | 7000
C_THZCE_PS_MEM_2 | 7000
C_THZCE_PS_MEM_3 | 7000
C_THZOE_PS_MEM_0 | 25000
C_THZOE_PS_MEM_1 | 7000
C_THZOE_PS_MEM_2 | 7000
C_THZOE_PS_MEM_3 | 7000
C_TLZWE_PS_MEM_0 | 5000
C_TLZWE_PS_MEM_1 | 0
C_TLZWE_PS_MEM_2 | 0
C_TLZWE_PS_MEM_3 | 0
C_TPACC_PS_FLASH_0 | 25000
C_TPACC_PS_FLASH_1 | 25000
C_TPACC_PS_FLASH_2 | 25000
C_TPACC_PS_FLASH_3 | 25000
C_TWC_PS_MEM_0 | 70000
C_TWC_PS_MEM_1 | 15000
C_TWC_PS_MEM_2 | 15000
C_TWC_PS_MEM_3 | 15000
C_TWP_PS_MEM_0 | 45000
C_TWP_PS_MEM_1 | 12000
C_TWP_PS_MEM_2 | 12000
C_TWP_PS_MEM_3 | 12000
C_XCL0_LINESIZE | 4
C_XCL0_WRITEXFER | 1
C_XCL1_LINESIZE | 4
C_XCL1_WRITEXFER | 1
C_XCL2_LINESIZE | 4
C_XCL2_WRITEXFER | 1
C_XCL3_LINESIZE | 4
C_XCL3_WRITEXFER | 1

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Peripherals | TOC
--- | ---

xps_ether_0 XPS LocalLink Tri-mode Ethernet MAC

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_ll_temac | 2.03.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | TemacIntc0_Irpt | O | 1 | xps_ether_0_TemacIntc0_Irpt
1 | TemacPhy_RST_n | O | 1 | fpga_0_xps_ether_0_TemacPhy_RST_n_pin
2 | GTX_CLK_0 | I | 1 | clk_125_0000MHzDCM0
3 | REFCLK | I | 1 | clk_200_0000MHz
4 | LlinkTemac0_CLK | I | 1 | clk_62_5000MHz
5 | MII_TX_CLK_0 | I | 1 | fpga_0_xps_ether_0_MII_TX_CLK_0_pin
6 | GMII_TXD_0 | O | 1 | fpga_0_xps_ether_0_GMII_TXD_0_pin
7 | GMII_TX_EN_0 | O | 1 | fpga_0_xps_ether_0_GMII_TX_EN_0_pin
8 | GMII_TX_ER_0 | O | 1 | fpga_0_xps_ether_0_GMII_TX_ER_0_pin
9 | GMII_TX_CLK_0 | O | 1 | fpga_0_xps_ether_0_GMII_TX_CLK_0_pin
10 | GMII_RXD_0 | I | 1 | fpga_0_xps_ether_0_GMII_RXD_0_pin
11 | GMII_RX_DV_0 | I | 1 | fpga_0_xps_ether_0_GMII_RX_DV_0_pin
12 | GMII_RX_ER_0 | I | 1 | fpga_0_xps_ether_0_GMII_RX_ER_0_pin
13 | GMII_RX_CLK_0 | I | 1 | fpga_0_xps_ether_0_GMII_RX_CLK_0_pin
14 | MDC_0 | O | 1 | fpga_0_xps_ether_0_MDC_0_pin
15 | MDIO_0 | IO | 1 | fpga_0_xps_ether_0_MDIO_0_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
LLINK0 | INITIATOR | XIL_LL_DMA | xps_ether_0_LLINK0 | mpmc_0
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x88F00000
C_HIGHADDR | 0x88F7FFFF
C_BUS2CORE_CLK_RATIO | 1
C_IDELAYCTRL_LOC | NOT_SET
C_INCLUDE_IO | 1
C_NUM_IDELAYCTRL | 0
C_PHY_TYPE | 1
C_RESERVED | 0
C_SIMULATION | 0
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 3
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 8
C_SPLB_P2P | 0
C_SUBFAMILY | FX
C_TEMAC0_AVB | 0
C_TEMAC0_MCAST_EXTEND | 0
C_TEMAC0_PHYADDR | 0b00001
C_TEMAC0_RXCSUM | 0
C_TEMAC0_RXFIFO | 2048
C_TEMAC0_RXVLAN_STRP | 0
C_TEMAC0_RXVLAN_TAG | 0

Name | Value
C_TEMAC0_RXVLAN_TRAN | 0
C_TEMAC0_STATS | 0
C_TEMAC0_TXCSUM | 0
C_TEMAC0_TXFIFO | 2048
C_TEMAC0_TXVLAN_STRP | 0
C_TEMAC0_TXVLAN_TAG | 0
C_TEMAC0_TXVLAN_TRAN | 0
C_TEMAC1_AVB | 0
C_TEMAC1_ENABLED | 0
C_TEMAC1_MCAST_EXTEND | 0
C_TEMAC1_PHYADDR | 0b00010
C_TEMAC1_RXCSUM | 0
C_TEMAC1_RXFIFO | 4096
C_TEMAC1_RXVLAN_STRP | 0
C_TEMAC1_RXVLAN_TAG | 0
C_TEMAC1_RXVLAN_TRAN | 0
C_TEMAC1_STATS | 0
C_TEMAC1_TXCSUM | 0
C_TEMAC1_TXFIFO | 4096
C_TEMAC1_TXVLAN_STRP | 0
C_TEMAC1_TXVLAN_TAG | 0
C_TEMAC1_TXVLAN_TRAN | 0
C_TEMAC_TYPE | 2

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

xps_gpio_0 XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_gpio | 2.00.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | GPIO_IO_O | O | 1 | internal_reset_request
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x80FF0000
C_HIGHADDR | 0x80FFFFFF
C_ALL_INPUTS | 0
C_ALL_INPUTS_2 | 0
C_DOUT_DEFAULT | 0x00000000
C_DOUT_DEFAULT_2 | 0x00000000
C_GPIO2_WIDTH | 32
C_GPIO_WIDTH | 1
C_INTERRUPT_PRESENT | 0

Name | Value
C_IS_DUAL | 0
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 1
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 1
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0
C_TRI_DEFAULT | 0xFFFFFFFF
C_TRI_DEFAULT_2 | 0xFFFFFFFF

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

xps_gpio_1 XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_gpio | 2.00.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | GPIO_IO_I | I | 1 | fpga_0_xps_gpio_1_GPIO_IO_I_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x80FE0000
C_HIGHADDR | 0x80FEFFFF
C_ALL_INPUTS | 1
C_ALL_INPUTS_2 | 0
C_DOUT_DEFAULT | 0x00000000
C_DOUT_DEFAULT_2 | 0x00000000
C_GPIO2_WIDTH | 32
C_GPIO_WIDTH | 4
C_INTERRUPT_PRESENT | 0

Name | Value
C_IS_DUAL | 0
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 1
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 1
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0
C_TRI_DEFAULT | 0xFFFFFFFF
C_TRI_DEFAULT_2 | 0xFFFFFFFF

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

xps_gpio_2 XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_gpio | 2.00.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | GPIO_IO_I | I | 1 | fpga_0_xps_gpio_2_GPIO_IO_I_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x80FD0000
C_HIGHADDR | 0x80FDFFFF
C_ALL_INPUTS | 1
C_ALL_INPUTS_2 | 0
C_DOUT_DEFAULT | 0x00000000
C_DOUT_DEFAULT_2 | 0x00000000
C_GPIO2_WIDTH | 32
C_GPIO_WIDTH | 8
C_INTERRUPT_PRESENT | 0

Name | Value
C_IS_DUAL | 0
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 1
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 1
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0
C_TRI_DEFAULT | 0xFFFFFFFF
C_TRI_DEFAULT_2 | 0xFFFFFFFF

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

xps_gpio_3 XPS General Purpose IO General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_gpio | 2.00.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | GPIO_IO_O | O | 1 | fpga_0_xps_gpio_3_GPIO_IO_O_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x80FC0000
C_HIGHADDR | 0x80FCFFFF
C_ALL_INPUTS | 0
C_ALL_INPUTS_2 | 0
C_DOUT_DEFAULT | 0x00000000
C_DOUT_DEFAULT_2 | 0x00000000
C_GPIO2_WIDTH | 32
C_GPIO_WIDTH | 8
C_INTERRUPT_PRESENT | 0

Name | Value
C_IS_DUAL | 0
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 1
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 1
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0
C_TRI_DEFAULT | 0xFFFFFFFF
C_TRI_DEFAULT_2 | 0xFFFFFFFF

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

xps_timer_0 XPS Timer/Counter Timer counter with PLBV46 interface

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_timer | 1.01.b | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | Interrupt | O | 1 | xps_timer_0_Interrupt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x8AEF0000
C_HIGHADDR | 0x8AEFFFFF
C_COUNT_WIDTH | 32
C_GEN0_ASSERT | 1
C_GEN1_ASSERT | 1
C_ONE_TIMER_ONLY | 0
C_SPLB_AWIDTH | 32

Name | Value
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 3
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 8
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0
C_TRIG0_ASSERT | 1
C_TRIG1_ASSERT | 1

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

xps_uart_0 XPS UART (16550-style) PLBV46 16550/450 UART (Universal Asynchronous Receiver/Transmitter)

IP Specs
Core | Version | Documentation
--- | --- | ---
xps_uart16550 | 3.00.a | IP | DRIVER

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | sin | I | 1 | fpga_0_xps_uart_0_sin_pin
1 | sout | O | 1 | fpga_0_xps_uart_0_sout_pin
2 | IP2INTC_Irpt | O | 1 | xps_uart_0_IP2INTC_Irpt
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Point 2 Point
SPLB | SLAVE | PLBV46 | mb_plb | microblaze_0

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_BASEADDR | 0x89FF0000
C_HIGHADDR | 0x89FFFFFF
C_EXTERNAL_XIN_CLK_HZ | 25000000
C_HAS_EXTERNAL_RCLK | 0
C_HAS_EXTERNAL_XIN | 0
C_IS_A_16550 | 1

Name | Value
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_MID_WIDTH | 1
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_NUM_MASTERS | 1
C_SPLB_P2P | 0
C_SPLB_SUPPORT_BURSTS | 0

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

IP | TOC
--- | ---

clock_generator_0 Clock Generator Clock generator for processor system.

IP Specs
Core | Version | Documentation
--- | --- | ---
clock_generator | 3.02.a | IP

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | CLKIN | I | 1 | dcm_clk_s
1 | CLKOUT0 | O | 1 | clk_125_0000MHz90DCM0
2 | CLKOUT1 | O | 1 | clk_125_0000MHzDCM0
3 | CLKOUT2 | O | 1 | clk_200_0000MHz
4 | CLKOUT3 | O | 1 | clk_62_5000MHz
5 | RST | I | 1 | sys_rst_s
6 | LOCKED | O | 1 | Dcm_all_locked

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.

Name | Value
C_FAMILY | virtex5
C_CLKFBIN_DESKEW | NONE
C_CLKFBIN_FREQ | 0
C_CLKFBOUT_BUF | TRUE
C_CLKFBOUT_FREQ | 0
C_CLKFBOUT_GROUP | NONE
C_CLKFBOUT_MODULE | NONE
C_CLKFBOUT_PHASE | 0
C_CLKFBOUT_PORT | NONE
C_CLKIN_FREQ | 125000000
C_CLKOUT0_BUF | TRUE
C_CLKOUT0_FREQ | 125000000
C_CLKOUT0_GROUP | DCM0
C_CLKOUT0_MODULE | NONE
C_CLKOUT0_PHASE | 90
C_CLKOUT0_PORT | NONE
C_CLKOUT0_VARIABLE_PHASE | FALSE
C_CLKOUT10_BUF | TRUE
C_CLKOUT10_FREQ | 0
C_CLKOUT10_GROUP | NONE
C_CLKOUT10_MODULE | NONE
C_CLKOUT10_PHASE | 0
C_CLKOUT10_PORT | NONE
C_CLKOUT10_VARIABLE_PHASE | FALSE
C_CLKOUT11_BUF | TRUE
C_CLKOUT11_FREQ | 0
C_CLKOUT11_GROUP | NONE
C_CLKOUT11_MODULE | NONE
C_CLKOUT11_PHASE | 0
C_CLKOUT11_PORT | NONE
C_CLKOUT11_VARIABLE_PHASE | FALSE
C_CLKOUT12_BUF | TRUE
C_CLKOUT12_FREQ | 0
C_CLKOUT12_GROUP | NONE
C_CLKOUT12_MODULE | NONE
C_CLKOUT12_PHASE | 0
C_CLKOUT12_PORT | NONE
C_CLKOUT12_VARIABLE_PHASE | FALSE
C_CLKOUT13_BUF | TRUE
C_CLKOUT13_FREQ | 0
C_CLKOUT13_GROUP | NONE
C_CLKOUT13_MODULE | NONE
C_CLKOUT13_PHASE | 0
C_CLKOUT13_PORT | NONE
C_CLKOUT13_VARIABLE_PHASE | FALSE
C_CLKOUT14_BUF | TRUE
C_CLKOUT14_FREQ | 0
C_CLKOUT14_GROUP | NONE
C_CLKOUT14_MODULE | NONE
C_CLKOUT14_PHASE | 0
C_CLKOUT14_PORT | NONE
C_CLKOUT14_VARIABLE_PHASE | FALSE
C_CLKOUT15_BUF | TRUE
C_CLKOUT15_FREQ | 0
C_CLKOUT15_GROUP | NONE
C_CLKOUT15_MODULE | NONE
C_CLKOUT15_PHASE | 0
C_CLKOUT15_PORT | NONE
C_CLKOUT15_VARIABLE_PHASE | FALSE
C_CLKOUT1_BUF | TRUE
C_CLKOUT1_FREQ | 125000000
C_CLKOUT1_GROUP | DCM0
C_CLKOUT1_MODULE | NONE
C_CLKOUT1_PHASE | 0
C_CLKOUT1_PORT | NONE
C_CLKOUT1_VARIABLE_PHASE | FALSE
C_CLKOUT2_BUF | TRUE
C_CLKOUT2_FREQ | 200000000
C_CLKOUT2_GROUP | NONE
C_CLKOUT2_MODULE | NONE
C_CLKOUT2_PHASE | 0
C_CLKOUT2_PORT | NONE
C_CLKOUT2_VARIABLE_PHASE | FALSE
C_CLKOUT3_BUF | TRUE
C_CLKOUT3_FREQ | 62500000
C_CLKOUT3_GROUP | NONE
C_CLKOUT3_MODULE | NONE
C_CLKOUT3_PHASE | 0
C_CLKOUT3_PORT | NONE
C_CLKOUT3_VARIABLE_PHASE | FALSE
C_CLKOUT4_BUF | TRUE
C_CLKOUT4_FREQ | 0
C_CLKOUT4_GROUP | NONE
C_CLKOUT4_MODULE | NONE
C_CLKOUT4_PHASE | 0
C_CLKOUT4_PORT | NONE
C_CLKOUT4_VARIABLE_PHASE | FALSE
C_CLKOUT5_BUF | TRUE
C_CLKOUT5_FREQ | 0
C_CLKOUT5_GROUP | NONE
C_CLKOUT5_MODULE | NONE
C_CLKOUT5_PHASE | 0
C_CLKOUT5_PORT | NONE
C_CLKOUT5_VARIABLE_PHASE | FALSE
C_CLKOUT6_BUF | TRUE
C_CLKOUT6_FREQ | 0
C_CLKOUT6_GROUP | NONE
C_CLKOUT6_MODULE | NONE
C_CLKOUT6_PHASE | 0
C_CLKOUT6_PORT | NONE
C_CLKOUT6_VARIABLE_PHASE | FALSE
C_CLKOUT7_BUF | TRUE
C_CLKOUT7_FREQ | 0
C_CLKOUT7_GROUP | NONE
C_CLKOUT7_MODULE | NONE
C_CLKOUT7_PHASE | 0
C_CLKOUT7_PORT | NONE
C_CLKOUT7_VARIABLE_PHASE | FALSE
C_CLKOUT8_BUF | TRUE
C_CLKOUT8_FREQ | 0
C_CLKOUT8_GROUP | NONE
C_CLKOUT8_MODULE | NONE
C_CLKOUT8_PHASE | 0
C_CLKOUT8_PORT | NONE
C_CLKOUT8_VARIABLE_PHASE | FALSE
C_CLKOUT9_BUF | TRUE
C_CLKOUT9_FREQ | 0
C_CLKOUT9_GROUP | NONE
C_CLKOUT9_MODULE | NONE
C_CLKOUT9_PHASE | 0
C_CLKOUT9_PORT | NONE
C_CLKOUT9_VARIABLE_PHASE | FALSE
C_CLK_GEN | update
C_DCM0_CLK0_BUF | false
C_DCM0_CLK180_BUF | false
C_DCM0_CLK270_BUF | false
C_DCM0_CLK2X180_BUF | false
C_DCM0_CLK2X_BUF | false
C_DCM0_CLK90_BUF | false
C_DCM0_CLKDV180_BUF | false
C_DCM0_CLKDV_BUF | false
C_DCM0_CLKDV_DIVIDE | 2.000000
C_DCM0_CLKFB_BUF | false
C_DCM0_CLKFB_MODULE | NONE
C_DCM0_CLKFB_PORT | NONE
C_DCM0_CLKFX180_BUF | false
C_DCM0_CLKFX_BUF | false
C_DCM0_CLKFX_DIVIDE | 1
C_DCM0_CLKFX_MULTIPLY | 4
C_DCM0_CLKIN_BUF | false
C_DCM0_CLKIN_DIVIDE_BY_2 | false
C_DCM0_CLKIN_MODULE | NONE
C_DCM0_CLKIN_PERIOD | 0.000000
C_DCM0_CLKIN_PORT | NONE
C_DCM0_CLKOUT_PHASE_SHIFT | NONE
C_DCM0_CLK_FEEDBACK | 1X
C_DCM0_DESKEW_ADJUST | SYSTEM_SYNCHRONOUS
C_DCM0_DFS_FREQUENCY_MODE | LOW
C_DCM0_DLL_FREQUENCY_MODE | LOW
C_DCM0_DSS_MODE | NONE
C_DCM0_DUTY_CYCLE_CORRECTION | true
C_DCM0_EXT_RESET_HIGH | 1
C_DCM0_FAMILY | virtex5
C_DCM0_PHASE_SHIFT | 0
C_DCM0_RST_MODULE | NONE
C_DCM0_STARTUP_WAIT | false
C_DCM1_CLK0_BUF | false
C_DCM1_CLK180_BUF | false
C_DCM1_CLK270_BUF | false
C_DCM1_CLK2X180_BUF | false
C_DCM1_CLK2X_BUF | false
C_DCM1_CLK90_BUF | false
C_DCM1_CLKDV180_BUF | false
C_DCM1_CLKDV_BUF | false
C_DCM1_CLKDV_DIVIDE | 2.000000
C_DCM1_CLKFB_BUF | false
C_DCM1_CLKFB_MODULE | NONE
C_DCM1_CLKFB_PORT | NONE
C_DCM1_CLKFX180_BUF | false
C_DCM1_CLKFX_BUF | false
C_DCM1_CLKFX_DIVIDE | 1
C_DCM1_CLKFX_MULTIPLY | 4
C_DCM1_CLKIN_BUF | false
C_DCM1_CLKIN_DIVIDE_BY_2 | false
C_DCM1_CLKIN_MODULE | NONE
C_DCM1_CLKIN_PERIOD | 0.000000
C_DCM1_CLKIN_PORT | NONE
C_DCM1_CLKOUT_PHASE_SHIFT | NONE
C_DCM1_CLK_FEEDBACK | 1X
C_DCM1_DESKEW_ADJUST | SYSTEM_SYNCHRONOUS
C_DCM1_DFS_FREQUENCY_MODE | LOW
C_DCM1_DLL_FREQUENCY_MODE | LOW
C_DCM1_DSS_MODE | NONE
C_DCM1_DUTY_CYCLE_CORRECTION | true
C_DCM1_EXT_RESET_HIGH | 1
C_DCM1_FAMILY | virtex5
C_DCM1_PHASE_SHIFT | 0
C_DCM1_RST_MODULE | NONE
C_DCM1_STARTUP_WAIT | false
C_DCM2_CLK0_BUF | false
C_DCM2_CLK180_BUF | false
C_DCM2_CLK270_BUF | false
C_DCM2_CLK2X180_BUF | false
C_DCM2_CLK2X_BUF | false
C_DCM2_CLK90_BUF | false
C_DCM2_CLKDV180_BUF | false
C_DCM2_CLKDV_BUF | false
C_DCM2_CLKDV_DIVIDE | 2.000000
C_DCM2_CLKFB_BUF | false
C_DCM2_CLKFB_MODULE | NONE
C_DCM2_CLKFB_PORT | NONE
C_DCM2_CLKFX180_BUF | false
C_DCM2_CLKFX_BUF | false
C_DCM2_CLKFX_DIVIDE | 1
C_DCM2_CLKFX_MULTIPLY | 4
C_DCM2_CLKIN_BUF | false
C_DCM2_CLKIN_DIVIDE_BY_2 | false
C_DCM2_CLKIN_MODULE | NONE
C_DCM2_CLKIN_PERIOD | 0.000000
C_DCM2_CLKIN_PORT | NONE
C_DCM2_CLKOUT_PHASE_SHIFT | NONE
C_DCM2_CLK_FEEDBACK | 1X
C_DCM2_DESKEW_ADJUST | SYSTEM_SYNCHRONOUS
C_DCM2_DFS_FREQUENCY_MODE | LOW
C_DCM2_DLL_FREQUENCY_MODE | LOW
C_DCM2_DSS_MODE | NONE
C_DCM2_DUTY_CYCLE_CORRECTION | true
C_DCM2_EXT_RESET_HIGH | 1
C_DCM2_FAMILY | virtex5
C_DCM2_PHASE_SHIFT | 0
C_DCM2_RST_MODULE | NONE
C_DCM2_STARTUP_WAIT | false
C_DCM3_CLK0_BUF | false
C_DCM3_CLK180_BUF | false
C_DCM3_CLK270_BUF | false
C_DCM3_CLK2X180_BUF | false
C_DCM3_CLK2X_BUF | false
C_DCM3_CLK90_BUF | false
C_DCM3_CLKDV180_BUF | false
C_DCM3_CLKDV_BUF | false
C_DCM3_CLKDV_DIVIDE | 2.000000
C_DCM3_CLKFB_BUF | false
C_DCM3_CLKFB_MODULE | NONE
C_DCM3_CLKFB_PORT | NONE
C_DCM3_CLKFX180_BUF | false
C_DCM3_CLKFX_BUF | false
C_DCM3_CLKFX_DIVIDE | 1
C_DCM3_CLKFX_MULTIPLY | 4
C_DCM3_CLKIN_BUF | false
C_DCM3_CLKIN_DIVIDE_BY_2 | false
C_DCM3_CLKIN_MODULE | NONE
C_DCM3_CLKIN_PERIOD | 0.000000
C_DCM3_CLKIN_PORT | NONE
C_DCM3_CLKOUT_PHASE_SHIFT | NONE
C_DCM3_CLK_FEEDBACK | 1X
C_DCM3_DESKEW_ADJUST | SYSTEM_SYNCHRONOUS
C_DCM3_DFS_FREQUENCY_MODE | LOW
C_DCM3_DLL_FREQUENCY_MODE | LOW
C_DCM3_DSS_MODE | NONE
C_DCM3_DUTY_CYCLE_CORRECTION | true
C_DCM3_EXT_RESET_HIGH | 1
C_DCM3_FAMILY | virtex5
C_DCM3_PHASE_SHIFT | 0
C_DCM3_RST_MODULE | NONE
C_DCM3_STARTUP_WAIT | false
C_EXT_RESET_HIGH | 0
C_MMCM0_BANDWIDTH | OPTIMIZED
C_MMCM0_CLKFBIN_MODULE | NONE
C_MMCM0_CLKFBIN_PORT | NONE
C_MMCM0_CLKFBOUT_BUF | false
C_MMCM0_CLKFBOUT_MULT_F | 1.000000
C_MMCM0_CLKFBOUT_PHASE | 0.000000
C_MMCM0_CLKFBOUT_USE_FINE_PS | false
C_MMCM0_CLKIN1_BUF | false
C_MMCM0_CLKIN1_MODULE | NONE
C_MMCM0_CLKIN1_PERIOD | 0.000000
C_MMCM0_CLKIN1_PORT | NONE
C_MMCM0_CLKOUT0_BUF | false
C_MMCM0_CLKOUT0_DIVIDE_F | 1.000000
C_MMCM0_CLKOUT0_DUTY_CYCLE | 0.500000
C_MMCM0_CLKOUT0_PHASE | 0.000000
C_MMCM0_CLKOUT0_USE_FINE_PS | false
C_MMCM0_CLKOUT1_BUF | false
C_MMCM0_CLKOUT1_DIVIDE | 1
C_MMCM0_CLKOUT1_DUTY_CYCLE | 0.500000
C_MMCM0_CLKOUT1_PHASE | 0.000000
C_MMCM0_CLKOUT1_USE_FINE_PS | false
C_MMCM0_CLKOUT2_BUF | false
C_MMCM0_CLKOUT2_DIVIDE | 1
C_MMCM0_CLKOUT2_DUTY_CYCLE | 0.500000
C_MMCM0_CLKOUT2_PHASE | 0.000000
C_MMCM0_CLKOUT2_USE_FINE_PS | false
C_MMCM0_CLKOUT3_BUF | false
C_MMCM0_CLKOUT3_DIVIDE | 1
C_MMCM0_CLKOUT3_DUTY_CYCLE | 0.500000
C_MMCM0_CLKOUT3_PHASE | 0.000000
C_MMCM0_CLKOUT3_USE_FINE_PS | false
C_MMCM0_CLKOUT4_BUF | false
C_MMCM0_CLKOUT4_CASCADE | false

Name | Value
C_MMCM0_CLKOUT4_DIVIDE | 1
C_MMCM0_CLKOUT4_DUTY_CYCLE | 0.500000
C_MMCM0_CLKOUT4_PHASE | 0.000000
C_MMCM0_CLKOUT4_USE_FINE_PS | false
C_MMCM0_CLKOUT5_BUF | false
C_MMCM0_CLKOUT5_DIVIDE | 1
C_MMCM0_CLKOUT5_DUTY_CYCLE | 0.500000
C_MMCM0_CLKOUT5_PHASE | 0.000000
C_MMCM0_CLKOUT5_USE_FINE_PS | false
C_MMCM0_CLKOUT6_BUF | false
C_MMCM0_CLKOUT6_DIVIDE | 1
C_MMCM0_CLKOUT6_DUTY_CYCLE | 0.500000
C_MMCM0_CLKOUT6_PHASE | 0.000000
C_MMCM0_CLKOUT6_USE_FINE_PS | false
C_MMCM0_CLOCK_HOLD | false
C_MMCM0_COMPENSATION | ZHOLD
C_MMCM0_DIVCLK_DIVIDE | 1
C_MMCM0_EXT_RESET_HIGH | 1
C_MMCM0_FAMILY | virtex6
C_MMCM0_REF_JITTER1 | 0.010000
C_MMCM0_RST_MODULE | NONE
C_MMCM0_STARTUP_WAIT | false
C_MMCM1_BANDWIDTH | OPTIMIZED
C_MMCM1_CLKFBIN_MODULE | NONE
C_MMCM1_CLKFBIN_PORT | NONE
C_MMCM1_CLKFBOUT_BUF | false
C_MMCM1_CLKFBOUT_MULT_F | 1.000000
C_MMCM1_CLKFBOUT_PHASE | 0.000000
C_MMCM1_CLKFBOUT_USE_FINE_PS | false
C_MMCM1_CLKIN1_BUF | false
C_MMCM1_CLKIN1_MODULE | NONE
C_MMCM1_CLKIN1_PERIOD | 0.000000
C_MMCM1_CLKIN1_PORT | NONE
C_MMCM1_CLKOUT0_BUF | false
C_MMCM1_CLKOUT0_DIVIDE_F | 1.000000
C_MMCM1_CLKOUT0_DUTY_CYCLE | 0.500000
C_MMCM1_CLKOUT0_PHASE | 0.000000
C_MMCM1_CLKOUT0_USE_FINE_PS | false
C_MMCM1_CLKOUT1_BUF | false
C_MMCM1_CLKOUT1_DIVIDE | 1
C_MMCM1_CLKOUT1_DUTY_CYCLE | 0.500000
C_MMCM1_CLKOUT1_PHASE | 0.000000
C_MMCM1_CLKOUT1_USE_FINE_PS | false
C_MMCM1_CLKOUT2_BUF | false
C_MMCM1_CLKOUT2_DIVIDE | 1
C_MMCM1_CLKOUT2_DUTY_CYCLE | 0.500000
C_MMCM1_CLKOUT2_PHASE | 0.000000
C_MMCM1_CLKOUT2_USE_FINE_PS | false
C_MMCM1_CLKOUT3_BUF | false
C_MMCM1_CLKOUT3_DIVIDE | 1
C_MMCM1_CLKOUT3_DUTY_CYCLE | 0.500000
C_MMCM1_CLKOUT3_PHASE | 0.000000
C_MMCM1_CLKOUT3_USE_FINE_PS | false
C_MMCM1_CLKOUT4_BUF | false
C_MMCM1_CLKOUT4_CASCADE | false
C_MMCM1_CLKOUT4_DIVIDE | 1
C_MMCM1_CLKOUT4_DUTY_CYCLE | 0.500000
C_MMCM1_CLKOUT4_PHASE | 0.000000
C_MMCM1_CLKOUT4_USE_FINE_PS | false
C_MMCM1_CLKOUT5_BUF | false
C_MMCM1_CLKOUT5_DIVIDE | 1
C_MMCM1_CLKOUT5_DUTY_CYCLE | 0.500000
C_MMCM1_CLKOUT5_PHASE | 0.000000
C_MMCM1_CLKOUT5_USE_FINE_PS | false
C_MMCM1_CLKOUT6_BUF | false
C_MMCM1_CLKOUT6_DIVIDE | 1
C_MMCM1_CLKOUT6_DUTY_CYCLE | 0.500000
C_MMCM1_CLKOUT6_PHASE | 0.000000
C_MMCM1_CLKOUT6_USE_FINE_PS | false
C_MMCM1_CLOCK_HOLD | false
C_MMCM1_COMPENSATION | ZHOLD
C_MMCM1_DIVCLK_DIVIDE | 1
C_MMCM1_EXT_RESET_HIGH | 1
C_MMCM1_FAMILY | virtex6
C_MMCM1_REF_JITTER1 | 0.010000
C_MMCM1_RST_MODULE | NONE
C_MMCM1_STARTUP_WAIT | false
C_MMCM2_BANDWIDTH | OPTIMIZED
C_MMCM2_CLKFBIN_MODULE | NONE
C_MMCM2_CLKFBIN_PORT | NONE
C_MMCM2_CLKFBOUT_BUF | false
C_MMCM2_CLKFBOUT_MULT_F | 1.000000
C_MMCM2_CLKFBOUT_PHASE | 0.000000
C_MMCM2_CLKFBOUT_USE_FINE_PS | false
C_MMCM2_CLKIN1_BUF | false
C_MMCM2_CLKIN1_MODULE | NONE
C_MMCM2_CLKIN1_PERIOD | 0.000000
C_MMCM2_CLKIN1_PORT | NONE
C_MMCM2_CLKOUT0_BUF | false
C_MMCM2_CLKOUT0_DIVIDE_F | 1.000000
C_MMCM2_CLKOUT0_DUTY_CYCLE | 0.500000
C_MMCM2_CLKOUT0_PHASE | 0.000000
C_MMCM2_CLKOUT0_USE_FINE_PS | false
C_MMCM2_CLKOUT1_BUF | false
C_MMCM2_CLKOUT1_DIVIDE | 1
C_MMCM2_CLKOUT1_DUTY_CYCLE | 0.500000
C_MMCM2_CLKOUT1_PHASE | 0.000000
C_MMCM2_CLKOUT1_USE_FINE_PS | false
C_MMCM2_CLKOUT2_BUF | false
C_MMCM2_CLKOUT2_DIVIDE | 1
C_MMCM2_CLKOUT2_DUTY_CYCLE | 0.500000
C_MMCM2_CLKOUT2_PHASE | 0.000000
C_MMCM2_CLKOUT2_USE_FINE_PS | false
C_MMCM2_CLKOUT3_BUF | false
C_MMCM2_CLKOUT3_DIVIDE | 1
C_MMCM2_CLKOUT3_DUTY_CYCLE | 0.500000
C_MMCM2_CLKOUT3_PHASE | 0.000000
C_MMCM2_CLKOUT3_USE_FINE_PS | false
C_MMCM2_CLKOUT4_BUF | false
C_MMCM2_CLKOUT4_CASCADE | false
C_MMCM2_CLKOUT4_DIVIDE | 1
C_MMCM2_CLKOUT4_DUTY_CYCLE | 0.500000
C_MMCM2_CLKOUT4_PHASE | 0.000000
C_MMCM2_CLKOUT4_USE_FINE_PS | false
C_MMCM2_CLKOUT5_BUF | false
C_MMCM2_CLKOUT5_DIVIDE | 1
C_MMCM2_CLKOUT5_DUTY_CYCLE | 0.500000
C_MMCM2_CLKOUT5_PHASE | 0.000000
C_MMCM2_CLKOUT5_USE_FINE_PS | false
C_MMCM2_CLKOUT6_BUF | false
C_MMCM2_CLKOUT6_DIVIDE | 1
C_MMCM2_CLKOUT6_DUTY_CYCLE | 0.500000
C_MMCM2_CLKOUT6_PHASE | 0.000000
C_MMCM2_CLKOUT6_USE_FINE_PS | false
C_MMCM2_CLOCK_HOLD | false
C_MMCM2_COMPENSATION | ZHOLD
C_MMCM2_DIVCLK_DIVIDE | 1
C_MMCM2_EXT_RESET_HIGH | 1
C_MMCM2_FAMILY | virtex6
C_MMCM2_REF_JITTER1 | 0.010000
C_MMCM2_RST_MODULE | NONE
C_MMCM2_STARTUP_WAIT | false
C_MMCM3_BANDWIDTH | OPTIMIZED
C_MMCM3_CLKFBIN_MODULE | NONE
C_MMCM3_CLKFBIN_PORT | NONE
C_MMCM3_CLKFBOUT_BUF | false
C_MMCM3_CLKFBOUT_MULT_F | 1.000000
C_MMCM3_CLKFBOUT_PHASE | 0.000000
C_MMCM3_CLKFBOUT_USE_FINE_PS | false
C_MMCM3_CLKIN1_BUF | false
C_MMCM3_CLKIN1_MODULE | NONE
C_MMCM3_CLKIN1_PERIOD | 0.000000
C_MMCM3_CLKIN1_PORT | NONE
C_MMCM3_CLKOUT0_BUF | false
C_MMCM3_CLKOUT0_DIVIDE_F | 1.000000
C_MMCM3_CLKOUT0_DUTY_CYCLE | 0.500000
C_MMCM3_CLKOUT0_PHASE | 0.000000
C_MMCM3_CLKOUT0_USE_FINE_PS | false
C_MMCM3_CLKOUT1_BUF | false
C_MMCM3_CLKOUT1_DIVIDE | 1
C_MMCM3_CLKOUT1_DUTY_CYCLE | 0.500000
C_MMCM3_CLKOUT1_PHASE | 0.000000
C_MMCM3_CLKOUT1_USE_FINE_PS | false
C_MMCM3_CLKOUT2_BUF | false
C_MMCM3_CLKOUT2_DIVIDE | 1
C_MMCM3_CLKOUT2_DUTY_CYCLE | 0.500000
C_MMCM3_CLKOUT2_PHASE | 0.000000
C_MMCM3_CLKOUT2_USE_FINE_PS | false
C_MMCM3_CLKOUT3_BUF | false
C_MMCM3_CLKOUT3_DIVIDE | 1
C_MMCM3_CLKOUT3_DUTY_CYCLE | 0.500000
C_MMCM3_CLKOUT3_PHASE | 0.000000
C_MMCM3_CLKOUT3_USE_FINE_PS | false
C_MMCM3_CLKOUT4_BUF | false
C_MMCM3_CLKOUT4_CASCADE | false
C_MMCM3_CLKOUT4_DIVIDE | 1
C_MMCM3_CLKOUT4_DUTY_CYCLE | 0.500000
C_MMCM3_CLKOUT4_PHASE | 0.000000
C_MMCM3_CLKOUT4_USE_FINE_PS | false
C_MMCM3_CLKOUT5_BUF | false
C_MMCM3_CLKOUT5_DIVIDE | 1
C_MMCM3_CLKOUT5_DUTY_CYCLE | 0.500000
C_MMCM3_CLKOUT5_PHASE | 0.000000
C_MMCM3_CLKOUT5_USE_FINE_PS | false
C_MMCM3_CLKOUT6_BUF | false
C_MMCM3_CLKOUT6_DIVIDE | 1
C_MMCM3_CLKOUT6_DUTY_CYCLE | 0.500000
C_MMCM3_CLKOUT6_PHASE | 0.000000
C_MMCM3_CLKOUT6_USE_FINE_PS | false
C_MMCM3_CLOCK_HOLD | false
C_MMCM3_COMPENSATION | ZHOLD
C_MMCM3_DIVCLK_DIVIDE | 1
C_MMCM3_EXT_RESET_HIGH | 1
C_MMCM3_FAMILY | virtex6
C_MMCM3_REF_JITTER1 | 0.010000
C_MMCM3_RST_MODULE | NONE
C_MMCM3_STARTUP_WAIT | false
C_PLL0_BANDWIDTH | OPTIMIZED
C_PLL0_CLKFBIN_MODULE | NONE
C_PLL0_CLKFBIN_PORT | NONE
C_PLL0_CLKFBOUT_BUF | false
C_PLL0_CLKFBOUT_DESKEW_ADJUST | NONE
C_PLL0_CLKFBOUT_MULT | 1
C_PLL0_CLKFBOUT_PHASE | 0.000000
C_PLL0_CLKIN1_BUF | false
C_PLL0_CLKIN1_MODULE | NONE
C_PLL0_CLKIN1_PERIOD | 0.000000
C_PLL0_CLKIN1_PORT | NONE
C_PLL0_CLKOUT0_BUF | false
C_PLL0_CLKOUT0_DESKEW_ADJUST | NONE
C_PLL0_CLKOUT0_DIVIDE | 1
C_PLL0_CLKOUT0_DUTY_CYCLE | 0.500000
C_PLL0_CLKOUT0_PHASE | 0.000000
C_PLL0_CLKOUT1_BUF | false
C_PLL0_CLKOUT1_DESKEW_ADJUST | NONE
C_PLL0_CLKOUT1_DIVIDE | 1
C_PLL0_CLKOUT1_DUTY_CYCLE | 0.500000
C_PLL0_CLKOUT1_PHASE | 0.000000
C_PLL0_CLKOUT2_BUF | false
C_PLL0_CLKOUT2_DESKEW_ADJUST | NONE
C_PLL0_CLKOUT2_DIVIDE | 1
C_PLL0_CLKOUT2_DUTY_CYCLE | 0.500000
C_PLL0_CLKOUT2_PHASE | 0.000000
C_PLL0_CLKOUT3_BUF | false
C_PLL0_CLKOUT3_DESKEW_ADJUST | NONE
C_PLL0_CLKOUT3_DIVIDE | 1
C_PLL0_CLKOUT3_DUTY_CYCLE | 0.500000
C_PLL0_CLKOUT3_PHASE | 0.000000
C_PLL0_CLKOUT4_BUF | false
C_PLL0_CLKOUT4_DESKEW_ADJUST | NONE
C_PLL0_CLKOUT4_DIVIDE | 1
C_PLL0_CLKOUT4_DUTY_CYCLE | 0.500000
C_PLL0_CLKOUT4_PHASE | 0.000000
C_PLL0_CLKOUT5_BUF | false
C_PLL0_CLKOUT5_DESKEW_ADJUST | NONE
C_PLL0_CLKOUT5_DIVIDE | 1
C_PLL0_CLKOUT5_DUTY_CYCLE | 0.500000
C_PLL0_CLKOUT5_PHASE | 0.000000
C_PLL0_COMPENSATION | SYSTEM_SYNCHRONOUS
C_PLL0_DIVCLK_DIVIDE | 1
C_PLL0_EXT_RESET_HIGH | 1
C_PLL0_FAMILY | virtex5
C_PLL0_REF_JITTER | 0.100000
C_PLL0_RESET_ON_LOSS_OF_LOCK | false
C_PLL0_RST_DEASSERT_CLK | CLKIN1
C_PLL0_RST_MODULE | NONE
C_PLL1_BANDWIDTH | OPTIMIZED
C_PLL1_CLKFBIN_MODULE | NONE
C_PLL1_CLKFBIN_PORT | NONE
C_PLL1_CLKFBOUT_BUF | false
C_PLL1_CLKFBOUT_DESKEW_ADJUST | NONE
C_PLL1_CLKFBOUT_MULT | 1
C_PLL1_CLKFBOUT_PHASE | 0.000000
C_PLL1_CLKIN1_BUF | false
C_PLL1_CLKIN1_MODULE | NONE
C_PLL1_CLKIN1_PERIOD | 0.000000
C_PLL1_CLKIN1_PORT | NONE
C_PLL1_CLKOUT0_BUF | false
C_PLL1_CLKOUT0_DESKEW_ADJUST | NONE
C_PLL1_CLKOUT0_DIVIDE | 1
C_PLL1_CLKOUT0_DUTY_CYCLE | 0.500000
C_PLL1_CLKOUT0_PHASE | 0.000000
C_PLL1_CLKOUT1_BUF | false
C_PLL1_CLKOUT1_DESKEW_ADJUST | NONE
C_PLL1_CLKOUT1_DIVIDE | 1
C_PLL1_CLKOUT1_DUTY_CYCLE | 0.500000
C_PLL1_CLKOUT1_PHASE | 0.000000
C_PLL1_CLKOUT2_BUF | false
C_PLL1_CLKOUT2_DESKEW_ADJUST | NONE
C_PLL1_CLKOUT2_DIVIDE | 1
C_PLL1_CLKOUT2_DUTY_CYCLE | 0.500000
C_PLL1_CLKOUT2_PHASE | 0.000000
C_PLL1_CLKOUT3_BUF | false
C_PLL1_CLKOUT3_DESKEW_ADJUST | NONE
C_PLL1_CLKOUT3_DIVIDE | 1
C_PLL1_CLKOUT3_DUTY_CYCLE | 0.500000
C_PLL1_CLKOUT3_PHASE | 0.000000
C_PLL1_CLKOUT4_BUF | false
C_PLL1_CLKOUT4_DESKEW_ADJUST | NONE
C_PLL1_CLKOUT4_DIVIDE | 1
C_PLL1_CLKOUT4_DUTY_CYCLE | 0.500000
C_PLL1_CLKOUT4_PHASE | 0.000000
C_PLL1_CLKOUT5_BUF | false
C_PLL1_CLKOUT5_DESKEW_ADJUST | NONE
C_PLL1_CLKOUT5_DIVIDE | 1
C_PLL1_CLKOUT5_DUTY_CYCLE | 0.500000
C_PLL1_CLKOUT5_PHASE | 0.000000
C_PLL1_COMPENSATION | SYSTEM_SYNCHRONOUS
C_PLL1_DIVCLK_DIVIDE | 1
C_PLL1_EXT_RESET_HIGH | 1
C_PLL1_FAMILY | virtex5
C_PLL1_REF_JITTER | 0.100000
C_PLL1_RESET_ON_LOSS_OF_LOCK | false
C_PLL1_RST_DEASSERT_CLK | CLKIN1
C_PLL1_RST_MODULE | NONE
C_PSDONE_GROUP | NONE
C_PSDONE_MODULE | NONE
C_SPEEDGRADE | 0

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

proc_sys_reset_0 Processor System Reset Module Reset management module

IP Specs
Core | Version | Documentation
--- | --- | ---
proc_sys_reset | 2.00.a | IP

PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
--- | --- | --- | --- | ---
0 | Slowest_sync_clk | I | 1 | clk_62_5000MHz
1 | Ext_Reset_In | I | 1 | sys_rst_s
2 | MB_Debug_Sys_Rst | I | 1 | Debug_SYS_Rst
3 | Dcm_locked | I | 1 | Dcm_all_locked
4 | MB_Reset | O | 1 | mb_reset
5 | Bus_Struct_Reset | O | 1 | sys_bus_reset
6 | Peripheral_Reset | O | 1 | sys_periph_reset
7 | Aux_Reset_In | I | 1 | internal_reset_request

Parameters
These are the current parameter settings for this module. Please refer to the IP documentation for complete information about module parameters. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex5
C_AUX_RESET_HIGH | 1
C_AUX_RST_WIDTH | 4
C_EXT_RESET_HIGH | 0
C_EXT_RST_WIDTH | 4
C_NUM_BUS_RST | 1
C_NUM_PERP_RST | 1
C_SUBFAMILY | lx

Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.

Timing Information | TOC
--- | ---

Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.