### Xilinx Processor IP Library

<hl>Software Drivers</hl>

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# xmpmc_hw.h File Reference

## Detailed Description

This header file contains identifiers and basic driver functions for the XMpmc device driver.

Note:
  None.

     MODIFICATION HISTORY:

     Ver   Who  Date     Changes
     ----- ---- -------- -----------------------------------------------
     1.00a mta  02/24/07 First release
     2.00a mta  10/24/07 Added support for Performance Monitoring and Static Phy
     3.00a sdm  12/16/08 Added support for debug registers

## Register offsets

#define | XMPMC_ECCCR_OFFSET
#define | XMPMC_ECCSR_OFFSET
#define | XMPMC_ECCSEC_OFFSET
#define | XMPMC_ECCDEC_OFFSET
#define | XMPMC_ECCPEC_OFFSET
#define | XMPMC_ECCADDR_OFFSET
#define | XMPMC_DGIE_OFFSET
#define | XMPMC_IPISR_OFFSET
#define | XMPMC_IPIER_OFFSET
#define | XMPMC_SPIR_OFFSET
#define | XMPMC_CALIB_RST_CTRL_OFFSET
#define | XMPMC_ECC_DEBUG_OFFSET
#define | XMPMC_ECC_READ_DATA_OFFSET
#define | XMPMC_ECC_WRITE_DATA_OFFSET
#define | XMPMC_S3_CALIB_REG_OFFSET
#define | XMPMC_S3_CALIB_STATUS_OFFSET
#define | XMPMC_V4_CALIB_REG_OFFSET
#define | XMPMC_V4_CALIB_STATUS_OFFSET
#define | XMPMC_V4_CALIB_DQS_GROUP0_OFFSET
#define | XMPMC_V4_CALIB_DQS_TAP_GROUP0_OFFSET
#define | XMPMC_V4_CALIB_DQ_TAP_CNT0_OFFSET
#define | XMPMC_V5_CALIB_REG_OFFSET
#define | XMPMC_V5_CALIB_STATUS_OFFSET
#define | XMPMC_V5_CALIB_DQS_GROUP0_OFFSET
#define | XMPMC_V5_CALIB_DQS_TAP_CNT0_OFFSET
#define | XMPMC_V5_CALIB_GATE_TAP_CNT0_OFFSET
#define | XMPMC_V5_CALIB_DQ_TAP_CNT0_OFFSET
#define | XMPMC_CTRL_STATUS_OFFSET
#define | XMPMC_PMCTRL_OFFSET
#define | XMPMC_PMCLR_OFFSET
#define | XMPMC_PMSTATUS_OFFSET
#define | XMPMC_PMGCC_OFFSET
#define | XMPMC_PMDCC_OFFSET
#define | XMPMC_PMDATABIN_OFFSET

## ECC Control Register bitmaps and masks

#define | XMPMC_ECCCR_FORCE_PE_MASK
#define | XMPMC_ECCCR_FORCE_DE_MASK
#define | XMPMC_ECCCR_FORCE_SE_MASK
#define | XMPMC_ECCCR_RE_MASK
#define | XMPMC_ECCCR_WE_MASK

## ECC Status Register bitmaps and masks

#define | XMPMC_ECCSR_ERR_SIZE_MASK
#define | XMPMC_ECCSR_ERR_RNW_MASK
#define | XMPMC_ECCSR_SE_SYND_MASK
#define | XMPMC_ECCSR_PE_MASK
#define | XMPMC_ECCSR_DE_MASK
#define | XMPMC_ECCSR_SE_MASK
#define | XMPMC_ECCSR_ERR_SIZE_SHIFT
#define | XMPMC_ECCSR_ERR_RNW_SHIFT
#define | XMPMC_ECCSR_SE_SYND_SHIFT

## Device Global Interrupt Enable Register bitmaps and masks

Bit definitions for the global interrupt enable register.
#define | XMPMC_DGIE_GIE_MASK

## Interrupt Status and Enable Register bitmaps and masks

Bit definitions for the interrupt status register and interrupt enable registers.
#define | XMPMC_IPIXR_PE_IX_MASK
#define | XMPMC_IPIXR_DE_IX_MASK
#define | XMPMC_IPIXR_SE_IX_MASK

## Static PHY Interface Register bitmaps and masks.

Bit definitions for the PHY Interface Register.
#define | XMPMC_SPIR_RDEN_DELAY_MASK
#define | XMPMC_SPIR_RDDATA_CLK_SEL_MASK
#define | XMPMC_SPIR_RDDATA_SWAP_RISE_MASK
#define | XMPMC_SPIR_FIRST_RST_DONE_MASK
#define | XMPMC_SPIR_DCM_PSEN_MASK
#define | XMPMC_SPIR_DCM_PSINCDEC_MASK
#define | XMPMC_SPIR_DCM_DONE_MASK
#define | XMPMC_SPIR_INIT_DONE_MASK
#define | XMPMC_SPIR_DCM_TAP_VALUE_MASK
#define | XMPMC_SPIR_RDEN_DELAY_SHIFT

## PM Control/Clear/Status Register bitmaps and masks

#define | XMPMC_PMREG_PM0_MASK
#define | XMPMC_PMREG_PM1_MASK
#define | XMPMC_PMREG_PM2_MASK
#define | XMPMC_PMREG_PM3_MASK
#define | XMPMC_PMREG_PM4_MASK
#define | XMPMC_PMREG_PM5_MASK
#define | XMPMC_PMREG_PM6_MASK
#define | XMPMC_PMREG_PM7_MASK
#define | XMPMC_PMREG_PM_ALL_MASK

## Calibration Reset Control Register bitmaps and masks

#define | XMPMC_CLB_RST_CTL_DEF_ON_RST_MASK

## ECC Debug Register bitmaps and masks

#define | XMPMC_ECC_DBG_BYTE_ACC_ENB_MASK

## ECC Read/Write Data Register bitmaps and masks

#define | XMPMC_ECC_RD_WR_DATA0_MASK
#define | XMPMC_ECC_RD_WR_DATA1_MASK
#define | XMPMC_ECC_RD_WR_DATA2_MASK
#define | XMPMC_ECC_RD_WR_DATA3_MASK

## Calibration Register bitmaps and masks

#define | XMPMC_S3CR_DQS_ENB_MASK
#define | XMPMC_S3CR_OUT_DQS_MASK
#define | XMPMC_S3CR_OUT_DQS_DIV_ENB_MASK
#define | XMPMC_S3CR_OUT_DQS_DIV_MASK
#define | XMPMC_V4CR_IDLY_CTL_RDYO_MASK
#define | XMPMC_V4CR_IDLY_CTL_RDY1_MASK
#define | XMPMC_V4CR_FRC_INIT_DONE_MASK
#define | XMPMC_V4CR_FRC_INIT_DONE_VAL_MASK
#define | XMPMC_V4CR_MIG_INIT_DONE_MASK
#define | XMPMC_V4CR_HW_CLB_ON_RST_MASK
#define | XMPMC_V5CR_IDLY_CTL_RDYO_MASK
#define | XMPMC_V5CR_IDLY_CTL_RDY1_MASK
#define | XMPMC_V5CR_FRC_INIT_DONE_MASK
#define | XMPMC_V5CR_FRC_INIT_DONE_VAL_MASK
#define | XMPMC_V5CR_MIG_INIT_DONE_MASK
#define | XMPMC_V5CR_HW_CLB_ON_RST_MASK

## Calibration Status Register bitmaps and masks

#define | XMPMC_S3CS_DBG_DEL_SEL_MASK
#define | XMPMC_S3CS_DBG_PHA_CNT_MASK
#define | XMPMC_S3CS_DBG_CNT_MASK
#define | XMPMC_S3CS_DBG_RST_CLB_MASK
#define | XMPMC_S3CS_DBG_TRANS_ONE_MASK
#define | XMPMC_S3CS_DBG_TRANS_TWO_MASK
#define | XMPMC_S3CS_DBG_ENB_TRANS_TWO_MASK
#define | XMPMC_V4CS_SEL_DONE_MASK
#define | XMPMC_V4CS_DONE_STS_MASK
#define | XMPMC_V4CS_ERR_STS_MASK
#define | XMPMC_V5CS_BIT_ERR_INDEX_MASK
#define | XMPMC_V5CS_DONE_STS_MASK
#define | XMPMC_V5CS_ERR_STS_MASK

## Calibration DQS Group Register bitmaps and masks

#define | XMPMC_V4CDG_BYTE_ALIGN_MASK
#define | XMPMC_V4CDG_RDEN_DLY_MASK
#define | XMPMC_V4CDG_DLY_RD_FALL_MASK
#define | XMPMC_V4CDG_RD_SEL_MASK
#define | XMPMC_V5CDG_RDEN_DLY_MASK
#define | XMPMC_V5CDG_GATE_DLY_MASK
#define | XMPMC_V5CDG_RD_SEL_MASK

## Calibration DQS Group Count Register bitmaps and masks

#define | XMPMC_V4CDQSTC_TAP_CNT_INC_MASK
#define | XMPMC_V4CDQSTC_TAP_CNT_DEC_MASK
#define | XMPMC_V4CDQSTC_TAP_CNT_MASK
#define | XMPMC_V5CDQSTC_TAP_CNT_INC_MASK
#define | XMPMC_V5CDQSTC_TAP_CNT_DEC_MASK
#define | XMPMC_V5CDQSTC_TAP_CNT_MASK

## Calibration DQ TAP Count Register bitmaps and masks

#define | XMPMC_V4CDQTC_TAP_CNT_INC_MASK
#define | XMPMC_V4CDQTC_TAP_CNT_DEC_MASK
#define | XMPMC_V4CDQTC_DLY_EN_MASK
#define | XMPMC_V4CDQTC_TAP_CNT_MASK
#define | XMPMC_V5CDQTC_TAP_CNT_INC_MASK
#define | XMPMC_V5CDQTC_TAP_CNT_DEC_MASK
#define | XMPMC_V5CDQTC_TAP_CNT_MASK

## Calibration Gate TAP Count Register bitmaps and masks

#define | XMPMC_V5CGTC_TAP_CNT_INC_MASK
#define | XMPMC_V5CGTC_TAP_CNT_DEC_MASK
#define | XMPMC_V5CGTC_TAP_CNT_MASK

## Definitions for the MPMC Control/Status register

#define | XMPMC_CSREG_ECC_CTRL_MASK
#define | XMPMC_CSREG_PHY_CTRL_MASK
#define | XMPMC_CSREG_DBG_CTRL_MASK
#define | XMPMC_CSREG_MPMC_CTRL_MASK
#define | XMPMC_CSREG_PM_CTRL_MASK
#define | XMPMC_CSREG_MEM_TYPE_MASK
#define | XMPMC_CSREG_MEM_WIDTH_MASK
#define | XMPMC_CSREG_NUM_PORTS_MASK
#define | XMPMC_CSREG_DEV_FAMILY_MASK

## Definitions for the Data bins registers of Performance Monitor

#define | XMPMC_PM_DATABIN_QUAL0
#define | XMPMC_PM_DATABIN_QUAL1
#define | XMPMC_PM_DATABIN_QUAL2
#define | XMPMC_PM_DATABIN_QUAL3
#define | XMPMC_PM_DATABIN_QUAL4
#define | XMPMC_PM_DATABIN_QUAL5
#define | XMPMC_PM_DATABIN_ACCESS_WRITE
#define | XMPMC_PM_DATABIN_ACCESS_READ
#define | XMPMC_PM_DATABIN_NUM_MIN
#define | XMPMC_PM_DATABIN_NUM_MAX
#define | XMPMC_PM_DATABIN_PORT_REG_OFFSET
#define | XMPMC_PM_DATABIN_QUAL_REG_OFFSET
#define | XMPMC_PM_DATABIN_ACCESS_REG_OFFSET

## Defines

#define | XMpmc_mWriteReg(BaseAddress, RegOffset, Data)
#define | XMpmc_mReadReg(BaseAddress, RegOffset)

## Define Documentation

#define XMPMC_CALIB_RST_CTRL_OFFSET

| Calibration Reset Control Reg

#define XMPMC_CLB_RST_CTL_DEF_ON_RST_MASK

| Register default on reset mask

#define XMPMC_CSREG_DBG_CTRL_MASK

| Debug Registers CTRL interface status

#define XMPMC_CSREG_DEV_FAMILY_MASK

| Device family

#define XMPMC_CSREG_ECC_CTRL_MASK

| ECC CTRL interface status

#define XMPMC_CSREG_MEM_TYPE_MASK

| Memory type (SDRAM/DDR/ DDR2)

#define XMPMC_CSREG_MEM_WIDTH_MASK

| External memory interface width

#define XMPMC_CSREG_MPMC_CTRL_MASK

| MPMC CTRL interface status

#define XMPMC_CSREG_NUM_PORTS_MASK

| Number of ports

#define XMPMC_CSREG_PHY_CTRL_MASK

| Static PHY CTRL interface status

#define XMPMC_CSREG_PM_CTRL_MASK

| PM CTRL interface status

#define XMPMC_CTRL_STATUS_OFFSET

| MPMC Control/Status Reg

#define XMPMC_DGIE_GIE_MASK

| Global Intr Enable

#define XMPMC_DGIE_OFFSET

| Device Global Interrupt Enable Reg

#define XMPMC_ECC_DBG_BYTE_ACC_ENB_MASK

| debug access to the ECC byte lane

#define XMPMC_ECC_DEBUG_OFFSET

| ECC Debug Register

#define XMPMC_ECC_RD_WR_DATA0_MASK

| Data read from ECC byte lane on the first byte of the data in the 4 beat memory burst

#define XMPMC_ECC_RD_WR_DATA1_MASK

| Data read from ECC byte lane on the second byte of the data in the 4 beat memory burst

#define XMPMC_ECC_RD_WR_DATA2_MASK

| Data read from ECC byte lane on the third byte of the data in the 4 beat memory burst

#define XMPMC_ECC_RD_WR_DATA3_MASK

| Data read from ECC byte lane on the fourth byte of the data in the 4 beat memory burst

#define XMPMC_ECC_READ_DATA_OFFSET

| ECC Read Data Register

#define XMPMC_ECC_WRITE_DATA_OFFSET

| ECC Write Data Register

#define XMPMC_ECCADDR_OFFSET

| ECC Error Address Register

#define XMPMC_ECCCR_FORCE_DE_MASK

| Force double bit error

#define XMPMC_ECCCR_FORCE_PE_MASK

| Force parity error

#define XMPMC_ECCCR_FORCE_SE_MASK

| Force single bit error

#define XMPMC_ECCCR_OFFSET

| ECC Control Register

#define XMPMC_ECCCR_RE_MASK

| ECC read enable

#define XMPMC_ECCCR_WE_MASK

| ECC write enable

#define XMPMC_ECCDEC_OFFSET

| ECC Double Error Count Register

#define XMPMC_ECCPEC_OFFSET

| ECC Parity Field Error Count Reg

#define XMPMC_ECCSEC_OFFSET

| ECC Single Error Count Register

#define XMPMC_ECCSR_DE_MASK

| Double bit error

#define XMPMC_ECCSR_ERR_RNW_MASK

| Error Transaction Rd/Wr

#define XMPMC_ECCSR_ERR_RNW_SHIFT

| Error Transc Rd/Wr shift

#define XMPMC_ECCSR_ERR_SIZE_MASK

| Error Transaction Size

#define XMPMC_ECCSR_ERR_SIZE_SHIFT

| Error Transaction shift

#define XMPMC_ECCSR_OFFSET

| ECC Status Register

#define XMPMC_ECCSR_PE_MASK

| Parity field bit error

#define XMPMC_ECCSR_SE_MASK

| Single bit error

#define XMPMC_ECCSR_SE_SYND_MASK

| Single bit error syndrome

#define XMPMC_ECCSR_SE_SYND_SHIFT

| Single error synd shift

#define XMPMC_IPIER_OFFSET

| IP Interrupt Enable Register

#define XMPMC_IPISR_OFFSET

| IP Interrupt Status Register

#define XMPMC_IPIXR_DE_IX_MASK

| Double bit error interrupt

#define XMPMC_IPIXR_PE_IX_MASK

| Parity field error interrupt

#define XMPMC_IPIXR_SE_IX_MASK

| Single bit error interrupt

#define XMpmc_mReadReg | ( | BaseAddress,
|  | RegOffset |  | ) |

Read a value from a MPMC register. A 32 bit read is performed.

Parameters:

  | BaseAddress | is the base address of the MPMC device.
  | RegOffset | is the register offset from the base to read from.

Returns:
  The value read from the register.

Note:
  C-style signature: u32 XMpmc_mReadReg(u32 BaseAddress, unsigned RegOffset);

#define XMpmc_mWriteReg | ( | BaseAddress,
|  | RegOffset,
|  | Data |  | ) |

Write a value to a MPMC register. A 32 bit write is performed.

Parameters:

  | BaseAddress | is the base address of the MPMC device.
  | RegOffset | is the register offset from the base to write to.
  | Data | is the data written to the register.

Returns:
  None.

Note:
  C-style signature: void XMpmc_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data);

#define XMPMC_PM_DATABIN_ACCESS_READ

| Read Access

#define XMPMC_PM_DATABIN_ACCESS_REG_OFFSET

| Address Offset between data bins of different Access types

#define XMPMC_PM_DATABIN_ACCESS_WRITE

| Write Access

#define XMPMC_PM_DATABIN_NUM_MAX

| Highest Bin Number

#define XMPMC_PM_DATABIN_NUM_MIN

| Lowest Bin Number

#define XMPMC_PM_DATABIN_PORT_REG_OFFSET

| Address Offset between data bins of different Ports

#define XMPMC_PM_DATABIN_QUAL0

| Qualifier 0 - Byte to Double words

#define XMPMC_PM_DATABIN_QUAL1

| Qualifier 1 - Cache Line 4

#define XMPMC_PM_DATABIN_QUAL2

| Qualifier 2 - Cache Line 8

#define XMPMC_PM_DATABIN_QUAL3

| Qualifier 3 - Burst 16

#define XMPMC_PM_DATABIN_QUAL4

| Qualifier 4 - Burst 32

#define XMPMC_PM_DATABIN_QUAL5

| Qualifier 5 - Burst 64

#define XMPMC_PM_DATABIN_QUAL_REG_OFFSET

| Address Offset between data bins of different Qualifiers

#define XMPMC_PMCLR_OFFSET

| PM Clear Register

#define XMPMC_PMCTRL_OFFSET

| PM Control Register

#define XMPMC_PMDATABIN_OFFSET

| PM Port-0 Data Bin-0 Register

#define XMPMC_PMDCC_OFFSET

| PM Dead Cycle Counter Port 0

#define XMPMC_PMGCC_OFFSET

| PM Global Cycle Counter Register

#define XMPMC_PMREG_PM0_MASK

| PM0 Mask

#define XMPMC_PMREG_PM1_MASK

| PM1 Mask

#define XMPMC_PMREG_PM2_MASK

| PM2 Mask

#define XMPMC_PMREG_PM3_MASK

| PM3 Mask

#define XMPMC_PMREG_PM4_MASK

| PM4 Mask

#define XMPMC_PMREG_PM5_MASK

| PM5 Mask

#define XMPMC_PMREG_PM6_MASK

| PM6 Mask

#define XMPMC_PMREG_PM7_MASK

| PM7 Mask

#define XMPMC_PMREG_PM_ALL_MASK

| PM All Mask

#define XMPMC_PMSTATUS_OFFSET

| PM Status Register

#define XMPMC_S3_CALIB_REG_OFFSET

| S3 Calibration Register

#define XMPMC_S3_CALIB_STATUS_OFFSET

| S3 Calibration Status Register

#define XMPMC_S3CR_DQS_ENB_MASK

| Enable signal for strobe tap selection

#define XMPMC_S3CR_OUT_DQS_DIV_ENB_MASK

| Enable signal for rst_dqs_div tap selection

#define XMPMC_S3CR_OUT_DQS_DIV_MASK

| Tap values for rst_dqs_div

#define XMPMC_S3CR_OUT_DQS_MASK

| Tap values for strobes

#define XMPMC_S3CS_DBG_CNT_MASK

| Counter used in the calibration logic

#define XMPMC_S3CS_DBG_DEL_SEL_MASK

| Tap value to delay the strobe and rst_dqs_div

#define XMPMC_S3CS_DBG_ENB_TRANS_TWO_MASK

| Enable signal for dbg_trans_two detect

#define XMPMC_S3CS_DBG_PHA_CNT_MASK

| Number of LUTs in the clock phase

#define XMPMC_S3CS_DBG_RST_CLB_MASK

| To stop new tap_values from calibration logic to strobe and rst_dqs_div during memory read operations

#define XMPMC_S3CS_DBG_TRANS_ONE_MASK

| Asserted when the first transition is detected

#define XMPMC_S3CS_DBG_TRANS_TWO_MASK

| Asserted when the second transition is detected

#define XMPMC_SPIR_DCM_DONE_MASK

| DCM Phase shift Done

#define XMPMC_SPIR_DCM_PSEN_MASK

| DCM Phase shift

#define XMPMC_SPIR_DCM_PSINCDEC_MASK

| DCM Phase shift Increment/Decrement

#define XMPMC_SPIR_DCM_TAP_VALUE_MASK

| DCM Tap Value Mask

#define XMPMC_SPIR_FIRST_RST_DONE_MASK

| First Reset of Phy

#define XMPMC_SPIR_INIT_DONE_MASK

| Init Done

#define XMPMC_SPIR_OFFSET

| Static Phy Control Register

#define XMPMC_SPIR_RDDATA_CLK_SEL_MASK

| Read Data Clk Edge

#define XMPMC_SPIR_RDDATA_SWAP_RISE_MASK

| Read Data Clk Shift

#define XMPMC_SPIR_RDEN_DELAY_MASK

| Read Enable Delay

#define XMPMC_SPIR_RDEN_DELAY_SHIFT

| Read Enable Delay

#define XMPMC_V4_CALIB_DQ_TAP_CNT0_OFFSET

| V4 Calibration DQ TAP Count0 Register

#define XMPMC_V4_CALIB_DQS_GROUP0_OFFSET

| V4 Calibration DQS Group0 Register

#define XMPMC_V4_CALIB_DQS_TAP_GROUP0_OFFSET

| V4 Calibration DQS TAP Count0 Register

#define XMPMC_V4_CALIB_REG_OFFSET

| V4 Calibration Register

#define XMPMC_V4_CALIB_STATUS_OFFSET

| V4 Calib Status Register

#define XMPMC_V4CDG_BYTE_ALIGN_MASK

| V4 Calibration bit alignment of 8 bits within the byte

#define XMPMC_V4CDG_DLY_RD_FALL_MASK

| Relative alignment of bytes for DQS group in V4

#define XMPMC_V4CDG_RD_SEL_MASK

| Final read capture MUX set for positive or negative edge capture for DQS group in V4

#define XMPMC_V4CDG_RDEN_DLY_MASK

| Number of cycles after read command until read data is valid for DQS group in V4

#define XMPMC_V4CDQSTC_TAP_CNT_DEC_MASK

| IDELAY tap count dec

#define XMPMC_V4CDQSTC_TAP_CNT_INC_MASK

| IDELAY tap count inc

#define XMPMC_V4CDQSTC_TAP_CNT_MASK

| IDELAY tap count

#define XMPMC_V4CDQTC_DLY_EN_MASK

| Delay enable

#define XMPMC_V4CDQTC_TAP_CNT_DEC_MASK

| IDELAY tap count dec

#define XMPMC_V4CDQTC_TAP_CNT_INC_MASK

| IDELAY tap count inc

#define XMPMC_V4CDQTC_TAP_CNT_MASK

| IDELAY tap count

#define XMPMC_V4CR_FRC_INIT_DONE_MASK

| V4 MPMC INIT DONE signal

#define XMPMC_V4CR_FRC_INIT_DONE_VAL_MASK

| V$ MPMC INIT DONE val when FORCE_INITDONE = 1

#define XMPMC_V4CR_HW_CLB_ON_RST_MASK

| V4 Hardware calibration on MPMC reset

#define XMPMC_V4CR_IDLY_CTL_RDY1_MASK

| V4 Status of MPMC_Idelayctrl_Rdy_I

#define XMPMC_V4CR_IDLY_CTL_RDYO_MASK

| V4 Status of MPMC_Idelayctrl_Rdy_O

#define XMPMC_V4CR_MIG_INIT_DONE_MASK

| V4 MIG h/w calibration initialization status

#define XMPMC_V4CS_DONE_STS_MASK

| V4 tap control and pattern compare calibration completion status (1 bit per dqs bit)

#define XMPMC_V4CS_ERR_STS_MASK

| V4 Pattern compare error completion status (1 bit per dqs bit)

#define XMPMC_V4CS_SEL_DONE_MASK

| V4 Calibration process of center-aligning DQS with respect to clock

#define XMPMC_V5_CALIB_DQ_TAP_CNT0_OFFSET

| Calibration DQ TAP Count0 Register

#define XMPMC_V5_CALIB_DQS_GROUP0_OFFSET

| V5 Calibration DQS Group0 Register

#define XMPMC_V5_CALIB_DQS_TAP_CNT0_OFFSET

| V5 Calibration DQS TAP Count0 Register

#define XMPMC_V5_CALIB_GATE_TAP_CNT0_OFFSET

| V5 Calibration GATE TAP Count0 Register

#define XMPMC_V5_CALIB_REG_OFFSET

| V5 Calibration Register

#define XMPMC_V5_CALIB_STATUS_OFFSET

| V5 Calib Status Register

#define XMPMC_V5CDG_GATE_DLY_MASK

| Number of cycles after read command until clock enable for DQ byte group is de-asserted to prevent post amble glitch for DQS group in V5

#define XMPMC_V5CDG_RD_SEL_MASK

| Final read capture MUX set for positive or negative edge capture for DQS group in V5

#define XMPMC_V5CDG_RDEN_DLY_MASK

| Number of cycles after read command until read data is valid for DQS group in V5

#define XMPMC_V5CDQSTC_TAP_CNT_DEC_MASK

| IDELAY tap count dec

#define XMPMC_V5CDQSTC_TAP_CNT_INC_MASK

| IDELAY tap count inc

#define XMPMC_V5CDQSTC_TAP_CNT_MASK

| IDELAY tap count

#define XMPMC_V5CDQTC_TAP_CNT_DEC_MASK

| IDELAY tap count dec

#define XMPMC_V5CDQTC_TAP_CNT_INC_MASK

| IDELAY tap count inc

#define XMPMC_V5CDQTC_TAP_CNT_MASK

| IDELAY tap count

#define XMPMC_V5CGTC_TAP_CNT_DEC_MASK

| IDELAY tap count dec

#define XMPMC_V5CGTC_TAP_CNT_INC_MASK

| IDELAY tap count inc

#define XMPMC_V5CGTC_TAP_CNT_MASK

| IDELAY tap count

#define XMPMC_V5CR_FRC_INIT_DONE_MASK

| V5 MPMC INIT DONE signal

#define XMPMC_V5CR_FRC_INIT_DONE_VAL_MASK

| V5 MPMC INIT DONE val when FORCE_INITDONE = 1

#define XMPMC_V5CR_HW_CLB_ON_RST_MASK

| V5 Hardware calibration on MPMC reset

#define XMPMC_V5CR_IDLY_CTL_RDY1_MASK

| V5 Status of MPMC_Idelayctrl_Rdy_I

#define XMPMC_V5CR_IDLY_CTL_RDYO_MASK

| V5 Status of MPMC_Idelayctrl_Rdy_O

#define XMPMC_V5CR_MIG_INIT_DONE_MASK

| V5 MIG h/w calibration initialization status

#define XMPMC_V5CS_BIT_ERR_INDEX_MASK

| Calibration error index

#define XMPMC_V5CS_DONE_STS_MASK

| V5 Calibration complete status

#define XMPMC_V5CS_ERR_STS_MASK

| V5 4-bit calibration error status

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