Direct registers | |
#define | XTE_RAF_OFFSET |
#define | XTE_TPF_OFFSET |
#define | XTE_IFGP_OFFSET |
#define | XTE_IS_OFFSET |
#define | XTE_IP_OFFSET |
#define | XTE_IE_OFFSET |
#define | XTE_TTAG_OFFSET |
#define | XTE_RTAG_OFFSET |
#define | XTE_MSW_OFFSET |
#define | XTE_LSW_OFFSET |
#define | XTE_CTL_OFFSET |
#define | XTE_RDY_OFFSET |
#define | XTE_UAWL_OFFSET |
#define | XTE_UAWU_OFFSET |
#define | XTE_TPID0_OFFSET |
#define | XTE_TPID1_OFFSET |
#define | XTE_TXBL_OFFSET |
#define | XTE_TXBU_OFFSET |
#define | XTE_RXBL_OFFSET |
#define | XTE_RXBU_OFFSET |
#define | XTE_RXUNDRL_OFFSET |
#define | XTE_RXUNDRU_OFFSET |
#define | XTE_RXFRAGL_OFFSET |
#define | XTE_RXFRAGU_OFFSET |
#define | XTE_RX64BL_OFFSET |
#define | XTE_RX64BU_OFFSET |
#define | XTE_RX65B127L_OFFSET |
#define | XTE_RX65B127U_OFFSET |
#define | XTE_RX128B255L_OFFSET |
#define | XTE_RX128B255U_OFFSET |
#define | XTE_RX256B511L_OFFSET |
#define | XTE_RX256B511U_OFFSET |
#define | XTE_RX512B1023L_OFFSET |
#define | XTE_RX512B1023U_OFFSET |
#define | XTE_RX1024BL_OFFSET |
#define | XTE_RX1024BU_OFFSET |
#define | XTE_RXOVRL_OFFSET |
#define | XTE_RXOVRU_OFFSET |
#define | XTE_TX64BL_OFFSET |
#define | XTE_TX64BU_OFFSET |
#define | XTE_TX65B127L_OFFSET |
#define | XTE_TX65B127U_OFFSET |
#define | XTE_TX128B255L_OFFSET |
#define | XTE_TX128B255U_OFFSET |
#define | XTE_TX256B511L_OFFSET |
#define | XTE_TX256B511U_OFFSET |
#define | XTE_TX512B1023L_OFFSET |
#define | XTE_TX512B1023U_OFFSET |
#define | XTE_TX1024L_OFFSET |
#define | XTE_TX1024U_OFFSET |
#define | XTE_TXOVRL_OFFSET |
#define | XTE_TXOVRU_OFFSET |
#define | XTE_RXFL_OFFSET |
#define | XTE_RXFU_OFFSET |
#define | XTE_RXFCSERL_OFFSET |
#define | XTE_RXFCSERU_OFFSET |
#define | XTE_RXBCSTFL_OFFSET |
#define | XTE_RXBCSTFU_OFFSET |
#define | XTE_RXMCSTFL_OFFSET |
#define | XTE_RXMCSTFU_OFFSET |
#define | XTE_RXCTRFL_OFFSET |
#define | XTE_RXCTRFU_OFFSET |
#define | XTE_RXLTERL_OFFSET |
#define | XTE_RXLTERU_OFFSET |
#define | XTE_RXVLANFL_OFFSET |
#define | XTE_RXVLANFU_OFFSET |
#define | XTE_RXPFL_OFFSET |
#define | XTE_RXPFU_OFFSET |
#define | XTE_RXUOPFL_OFFSET |
#define | XTE_RXUOPFU_OFFSET |
#define | XTE_TXFL_OFFSET |
#define | XTE_TXFU_OFFSET |
#define | XTE_TXBCSTFL_OFFSET |
#define | XTE_TXBCSTFU_OFFSET |
#define | XTE_TXMCSTFL_OFFSET |
#define | XTE_TXMCSTFU_OFFSET |
#define | XTE_TXUNDRERL_OFFSET |
#define | XTE_TXUNDRERU_OFFSET |
#define | XTE_TXCTRFL_OFFSET |
#define | XTE_TXCTRFU_OFFSET |
#define | XTE_TXVLANFL_OFFSET |
#define | XTE_TXVLANFU_OFFSET |
#define | XTE_TXPFL_OFFSET |
#define | XTE_TXPFU_OFFSET |
HARD_TEMAC Core Registers | |
These are registers defined within the device's hard core located in the processor block. They are accessed indirectly through the registers, MSW, LSW, and CTL.
Access to these registers should go through macros XLlTemac_ReadIndirectReg() and XLlTemac_WriteIndirectReg() to guarantee proper access. | |
#define | XTE_RCW0_OFFSET |
#define | XTE_RCW1_OFFSET |
#define | XTE_TC_OFFSET |
#define | XTE_FCC_OFFSET |
#define | XTE_EMMC_OFFSET |
#define | XTE_PHYC_OFFSET |
#define | XTE_MC_OFFSET |
#define | XTE_UAW0_OFFSET |
#define | XTE_UAW1_OFFSET |
#define | XTE_MAW0_OFFSET |
#define | XTE_MAW1_OFFSET |
#define | XTE_AFM_OFFSET |
#define | XTE_TIS_OFFSET |
#define | XTE_TIE_OFFSET |
#define | XTE_MIIMWD_OFFSET |
#define | XTE_MIIMAI_OFFSET |
Transmit VLAN Data Table | |
This offset defines an offset to table that has provisioned transmit VLAN data. It is stored in BRAM and will be used by hardware to provide transmit VLAN tag, strip, and translation. | |
#define | XTE_TX_VLAN_DATA_OFFSET |
Receive VLAN Data Table | |
This offset defines an offset to table that has provisioned receive VLAN data. It is stored in BRAM and will be used by hardware to provide receive VLAN tag, strip, and translation. | |
#define | XTE_RX_VLAN_DATA_OFFSET |
Extended Multicast Address Table | |
This offset defines an offset to table that has provisioned multicast addresses. It is stored in BRAM and will be used by hardware to provide first line of address matching when a multicast frame is reveived. It can minimize the use of CPU/software hence minimize performance impact. | |
#define | XTE_MCAST_BRAM_OFFSET |
Reset and Address Filter bits | |
These bits are associated with the XTE_RAF_OFFSET register. | |
#define | XTE_RAF_HTRST_MASK |
#define | XTE_RAF_MCSTREJ_MASK |
#define | XTE_RAF_BCSTREJ_MASK |
#define | XTE_RAF_TXVTAGMODE_MASK |
#define | XTE_RAF_RXVTAGMODE_MASK |
#define | XTE_RAF_TXVSTRPMODE_MASK |
#define | XTE_RAF_RXVSTRPMODE_MASK |
#define | XTE_RAF_NEWFNCENBL_MASK |
#define | XTE_RAF_EMULTIFLTRENBL_MASK |
#define | XTE_RAF_TXVTAGMODE_SHIFT |
#define | XTE_RAF_RXVTAGMODE_SHIFT |
#define | XTE_RAF_TXVSTRPMODE_SHIFT |
#define | XTE_RAF_RXVSTRPMODE_SHIFT |
Transmit Pause Frame Register (TPF) | |
#define | XTE_TPF_TPFV_MASK |
Transmit Inter-Frame Gap Adjustement Register (TFGP) | |
#define | XTE_TFGP_IFGP_MASK |
Interrupt bits | |
These bits are associated with the XTE_IS_OFFSET, XTE_IP_OFFSET, and XTE_IE_OFFSET registers. | |
#define | XTE_INT_HARDACSCMPLT_MASK |
#define | XTE_INT_AUTONEG_MASK |
#define | XTE_INT_RC_MASK |
#define | XTE_INT_RXRJECT_MASK |
#define | XTE_INT_RXFIFOOVR_MASK |
#define | XTE_INT_TC_MASK |
#define | XTE_INT_RXDCM_LOCK_MASK |
#define | XTE_INT_MGT_LOCK_MASK |
#define | XTE_INT_ALL_MASK |
Control Register (CTL) | |
#define | XTE_CTL_WEN_MASK |
TPID Register (TPID) | |
#define | XTE_TPID_0_MASK |
#define | XTE_TPID_1_MASK |
Ready Status, TEMAC Interrupt Status, TEMAC Interrupt Enable Registers | |
(RDY, TIS, TIE) | |
#define | XTE_RSE_FABR_RR_MASK |
#define | XTE_RSE_MIIM_RR_MASK |
#define | XTE_RSE_MIIM_WR_MASK |
#define | XTE_RSE_AF_RR_MASK |
#define | XTE_RSE_AF_WR_MASK |
#define | XTE_RSE_CFG_RR_MASK |
#define | XTE_RSE_CFG_WR_MASK |
#define | XTE_RDY_HARD_ACS_RDY_MASK |
#define | XTE_RDY_ALL |
Receive Configuration Word 1 (RCW1) | |
#define | XTE_RCW1_RST_MASK |
#define | XTE_RCW1_JUM_MASK |
#define | XTE_RCW1_FCS_MASK |
#define | XTE_RCW1_RX_MASK |
#define | XTE_RCW1_VLAN_MASK |
#define | XTE_RCW1_HD_MASK |
#define | XTE_RCW1_LT_DIS_MASK |
#define | XTE_RCW1_PAUSEADDR_MASK |
Transmitter Configuration (TC) | |
#define | XTE_TC_RST_MASK |
#define | XTE_TC_JUM_MASK |
#define | XTE_TC_FCS_MASK |
#define | XTE_TC_TX_MASK |
#define | XTE_TC_VLAN_MASK |
#define | XTE_TC_HD_MASK |
#define | XTE_TC_IFG_MASK |
Flow Control Configuration (FCC) | |
#define | XTE_FCC_FCRX_MASK |
#define | XTE_FCC_FCTX_MASK |
EMAC Configuration (EMMC) | |
#define | XTE_EMMC_LINKSPEED_MASK |
#define | XTE_EMMC_RGMII_MASK |
#define | XTE_EMMC_SGMII_MASK |
#define | XTE_EMMC_GPCS_MASK |
#define | XTE_EMMC_HOST_MASK |
#define | XTE_EMMC_TX16BIT |
#define | XTE_EMMC_RX16BIT |
#define | XTE_EMMC_LINKSPD_10 |
#define | XTE_EMMC_LINKSPD_100 |
#define | XTE_EMMC_LINKSPD_1000 |
EMAC RGMII/SGMII Configuration (PHYC) | |
#define | XTE_PHYC_SGMIILINKSPEED_MASK |
#define | XTE_PHYC_RGMIILINKSPEED_MASK |
#define | XTE_PHYC_RGMIIHD_MASK |
#define | XTE_PHYC_RGMIILINK_MASK |
#define | XTE_PHYC_RGLINKSPD_10 |
#define | XTE_PHYC_RGLINKSPD_100 |
#define | XTE_PHYC_RGLINKSPD_1000 |
#define | XTE_PHYC_SGLINKSPD_10 |
#define | XTE_PHYC_SGLINKSPD_100 |
#define | XTE_PHYC_SGLINKSPD_1000 |
EMAC Management Configuration (MC) | |
#define | XTE_MC_MDIOEN_MASK |
#define | XTE_MC_CLOCK_DIVIDE_MAX |
EMAC Unicast Address Register Word 1 (UAW1) | |
#define | XTE_UAW1_UNICASTADDR_MASK |
EMAC Multicast Address Register Word 1 (MAW1) | |
#define | XTE_MAW1_RNW_MASK |
#define | XTE_MAW1_ADDR_MASK |
#define | XTE_MAW1_MULTICADDR_MASK |
#define | XTE_MAW1_MATADDR_SHIFT_MASK |
EMAC Address Filter Mode (AFM) | |
#define | XTE_AFM_PM_MASK |
Media Independent Interface Management (MIIM) | |
#define | XTE_MIIM_REGAD_MASK |
#define | XTE_MIIM_PHYAD_MASK |
#define | XTE_MIIM_PHYAD_SHIFT |
Checksum offload buffer descriptor extensions | |
#define | XTE_BD_TX_CSBEGIN_OFFSET |
#define | XTE_BD_TX_CSINSERT_OFFSET |
#define | XTE_BD_TX_CSCNTRL_OFFSET |
#define | XTE_BD_TX_CSINIT_OFFSET |
#define | XTE_BD_RX_CSRAW_OFFSET |
TX_CSCNTRL bit mask | |
#define | XTE_BD_TX_CSCNTRL_CALC_MASK |
Defines | |
#define | XTE_RESET_HARD_DELAY_US |
#define | XTE_INT_RECV_ERROR_MASK |
#define | XLlTemac_ReadReg(BaseAddress, RegOffset) |
#define | XLlTemac_WriteReg(BaseAddress, RegOffset, Data) |
#define | XLlTemac_ReadIndirectReg(BaseAddress, RegOffset) |
#define | XLlTemac_WriteIndirectReg(BaseAddress, RegOffset, Data) |
|
XLlTemac_ReadIndirectReg returns the value read from the hard TEMAC register specified by RegOffset.
|
|
XLlTemac_ReadReg returns the value read from the register specified by RegOffset.
|
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XLlTemac_WriteIndirectReg, writes Data to the hard TEMAC register specified by RegOffset.
|
|
XLlTemac_WriteReg, writes Data to the register specified by RegOffset.
|
|
Address Filter (promiscuous) mode |
|
Promiscuous mode enable |
|
Receive frame checksum calculation (16 bit word) |
|
Byte offset where checksum should begin (16 bit word) |
|
Enable/disable Tx checksum |
|
Checksum offload control for transmit (16 bit word) |
|
Seed value for checksum calculation (16 bit word) |
|
Offset where checksum should be inserted (16 bit word) |
|
Control |
|
Write Enable |
|
1000BaseX mode enable |
|
Host interface enable |
|
XTE_EMCFG_LINKSPD_MASK for 10 Mbit |
|
XTE_EMCFG_LINKSPD_MASK for 100 Mbit |
|
XTE_EMCFG_LINKSPD_MASK for 1000 Mbit |
|
Link speed |
|
EMAC mode configuration |
|
RGMII mode enable |
|
16 bit Rx client enable |
|
SGMII mode enable |
|
16 bit Tx client enable |
|
Rx flow control enable |
|
Tx flow control enable |
|
Flow control configuration |
|
Interrupt enable |
|
Transmit inter-frame gap adjustment |
|
All the ints |
|
Auto negotiation complete |
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Hard register access complete |
|
MGT clock Lock |
|
Receive complete |
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INT bits that indicate receive errors |
|
Rx Dcm Lock |
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Receive fifo overrun |
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Receive frame rejected |
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Transmit complete |
|
Interrupt pending |
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Interrupt status |
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Least significant word data |
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Multicast address word 0 |
|
Multicast address table register address |
|
Number of bits to shift right to align with XTE_MAW1_CAMADDR_MASK |
|
Multicast address bits [47:32] Multicast address bits [31:0] are stored in register MAW0 |
|
Multicast address word 1 |
|
Multicast address table register read enable |
|
Maximum MDIO divisor |
|
MII management enable |
|
Management configuration |
|
multicast table address |
|
MII Phy address (PHYAD) |
|
MII Shift bits for PHYAD |
|
MII Phy register address (REGAD) |
|
MII management access initiate |
|
MII management write data |
|
Most significant word data |
|
RGMII/SGMII configuration |
|
XTE_GMIC_RGLINKSPD_MASK for 10 Mbit |
|
XTE_GMIC_RGLINKSPD_MASK for 100 Mbit |
|
XTE_GMIC_RGLINKSPD_MASK for 1000 Mbit |
|
RGMII Half-duplex mode |
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RGMII link status |
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RGMII link speed |
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XTE_SGMIC_RGLINKSPD_MASK for 10 Mbit |
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XTE_SGMIC_RGLINKSPD_MASK for 100 Mbit |
|
XTE_SGMIC_RGLINKSPD_MASK for 1000 Mbit |
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SGMII link speed |
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Reject receive broadcast destination address |
|
Exteneded Multicast Filtering mode |
|
Hard TEMAC Reset |
|
Reject receive multicast destination address |
|
New function mode |
|
Reset and address filter |
|
Rx VLAN STRIP mode |
|
Rx Strip mode shift bits |
|
Rx VLAN TAG mode |
|
Rx Tag mode shift bits |
|
Tx VLAN STRIP mode |
|
Tx strip mode shift bits |
|
Tx VLAN TAG mode |
|
Tx Tag mode shift bits |
|
Rx configuration word 0 |
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In-Band FCS enable (FCS not stripped) |
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Half duplex mode |
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Jumbo frame enable |
|
Length/type field valid check disable |
|
Rx configuration word 1 |
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Pause frame source address bits [47:32]. Bits [31:0] are stored in register RCW0 |
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Reset |
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Receiver enable |
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VLAN frame enable |
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Hard register access ready |
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Ready status |
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Us to delay for hard core reset |
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Address filter read ready |
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Address filter write ready |
|
Configuration register read ready |
|
Configuration register write ready |
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Fabric read ready |
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MII management read ready |
|
MII management write ready |
|
Rx VLAN TAG |
|
Frames count of 1024-MAX bytes frames received, least significant word |
|
Frames count of 1024-MAX bytes frames received, most significant word |
|
Frames count of 128-255 bytes frames received, least significant word |
|
Frames count of 128-255 bytes frames received, most significant word |
|
Frames count of 256-511 bytes frames received, least significant word |
|
Frames count of 256-511 bytes frames received, most significant word |
|
Frames count of 512-1023 bytes frames received, least significant word |
|
Frames count of 512-1023 bytes frames received, most significant word |
|
Frames count of 64 bytes frames received, least significant word |
|
Frames count of 64 bytes frames received, most significant word |
|
Frames count of 65-127 bytes frames received, least significant word |
|
Frames count of 65-127 bytes frames received, most significant word |
|
TX VLAN data table address |
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Frames count of broadcast frames received, least significant word |
|
Frames count of broadcast frames received, most significant word |
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Bytes count of received frames, least significant word |
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Bytes count of received frames, most significant word |
|
Frames count of control frames received, least significant word |
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Frames count of control frames received, most significant word |
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Frames count of frames received FCS error and at least 64 bytes, least significant word |
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Frames count of frames received FCS error and at least 64 bytes, most significant word |
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Frames count of frames received OK, least significant word |
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Frames count of undersized(less than 64 bytes) and bad FCS frames received, least significant word |
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Frames count of undersized(less than 64 bytes) and bad FCS frames received, most significant word |
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Frames count of frames received OK, most significant word |
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Frames count of frames received with length error, least significant word |
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Frames count of frames received with length error, most significant word |
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Frames count of multicast frames received, least significant word |
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Frames count of multicast frames received, most significant word |
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Frames count of oversize frames received, least significant word |
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Frames count of oversize frames received, most significant word |
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Frames count of pause frames received, least significant word |
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Frames count of pause frames received, most significant word |
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Frames count of undersize(less than 64 bytes) frames received, least significant word |
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Frames count of undersize(less than 64 bytes) frames received, most significant word |
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Frames count of control frames received with unsupported opcode, least significant word |
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Frames count of control frames received with unsupported opcode, most significant word |
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Frames count of VLAN tagged frames received, least significant word |
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Frames count of VLAN tagged frames received, most significant word |
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In-Band FCS enable (FCS not generated) |
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Half duplex mode |
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Inter-frame gap adjustment enable |
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Jumbo frame enable |
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Tx configuration |
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reset |
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Transmitter enable |
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VLAN frame enable |
|
Transmit inter-frame gap adjustment value |
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Interrupt enable |
|
Interrupt status |
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Transmit pause frame |
|
Tx pause frame value |
|
TPID0 register |
|
TPID1 register |
|
TPID 0 |
|
TPID 1 |
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Tx VLAN TAG |
|
Frames count of 1024-MAX bytes frames transmitted, least significant word |
|
Frames count of 1024-MAX bytes frames transmitted, most significant word |
|
Frames count of 128-255 bytes frames transmitted, least significant word |
|
Frames count of 128-255 bytes frames transmitted, most significant word |
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Frames count of 256-511 bytes frames transmittereceived, least significant word |
|
Frames count of 256-511 bytes frames transmitted, most significant word |
|
Frames count of 512-1023 bytes frames transmitted, least significant word |
|
Frames count of 512-1023 bytes frames transmitted, most significant word |
|
Frames count of 64 bytes frames transmitted, least significant word |
|
Frames count of 64 bytes frames transmitted, most significant word |
|
Frames count of 65-127 bytes frames transmitted, least significant word |
|
Frames count of 65-127 bytes frames transmitted, most significant word |
|
TX VLAN data table address |
|
Frames count of broadcast frames transmitted, least significant word |
|
Frames count of broadcast frames transmitted, most significant word |
|
Bytes count of transmitted frames, least significant word |
|
Bytes count of transmitted frames, most significant word |
|
Frames count of control frames transmitted, least significant word |
|
Frames count of control frames transmitted, most significant word |
|
Frames count of frames transmitted OK, least significant word |
|
Frames count of frames transmitted OK, most significant word |
|
Frames count of multicast frames transmitted, least significant word |
|
Frames count of multicast frames transmitted, most significant word |
|
Frames count of oversize frames transmitted, least significant word |
|
Frames count of oversize frames transmitted, most significant word |
|
Frames count of pause frames transmitted, least significant word |
|
Frames count of pause frames transmitted, most significant word |
|
Frames count of frames transmitted underrun error, least significant word |
|
Frames count of frames transmitted underrun error, most significant word |
|
Frames count of VLAN tagged frames transmitted, least significant word |
|
Frames count of VLAN tagged frames transmitted, most significant word |
|
Unicast address word 0 |
|
Unicast address word 1 |
|
Station address bits [47:32] Station address bits [31:0] are stored in register UAW0 |
|
Unicast address, extended/new multicast mode |
|
Unicast address, extended/new multicast mode |
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