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xlltemac_hw.h File Reference


Detailed Description


Direct registers

#define XTE_RAF_OFFSET
#define XTE_TPF_OFFSET
#define XTE_IFGP_OFFSET
#define XTE_IS_OFFSET
#define XTE_IP_OFFSET
#define XTE_IE_OFFSET
#define XTE_TTAG_OFFSET
#define XTE_RTAG_OFFSET
#define XTE_MSW_OFFSET
#define XTE_LSW_OFFSET
#define XTE_CTL_OFFSET
#define XTE_RDY_OFFSET
#define XTE_UAWL_OFFSET
#define XTE_UAWU_OFFSET
#define XTE_TPID0_OFFSET
#define XTE_TPID1_OFFSET
#define XTE_TXBL_OFFSET
#define XTE_TXBU_OFFSET
#define XTE_RXBL_OFFSET
#define XTE_RXBU_OFFSET
#define XTE_RXUNDRL_OFFSET
#define XTE_RXUNDRU_OFFSET
#define XTE_RXFRAGL_OFFSET
#define XTE_RXFRAGU_OFFSET
#define XTE_RX64BL_OFFSET
#define XTE_RX64BU_OFFSET
#define XTE_RX65B127L_OFFSET
#define XTE_RX65B127U_OFFSET
#define XTE_RX128B255L_OFFSET
#define XTE_RX128B255U_OFFSET
#define XTE_RX256B511L_OFFSET
#define XTE_RX256B511U_OFFSET
#define XTE_RX512B1023L_OFFSET
#define XTE_RX512B1023U_OFFSET
#define XTE_RX1024BL_OFFSET
#define XTE_RX1024BU_OFFSET
#define XTE_RXOVRL_OFFSET
#define XTE_RXOVRU_OFFSET
#define XTE_TX64BL_OFFSET
#define XTE_TX64BU_OFFSET
#define XTE_TX65B127L_OFFSET
#define XTE_TX65B127U_OFFSET
#define XTE_TX128B255L_OFFSET
#define XTE_TX128B255U_OFFSET
#define XTE_TX256B511L_OFFSET
#define XTE_TX256B511U_OFFSET
#define XTE_TX512B1023L_OFFSET
#define XTE_TX512B1023U_OFFSET
#define XTE_TX1024L_OFFSET
#define XTE_TX1024U_OFFSET
#define XTE_TXOVRL_OFFSET
#define XTE_TXOVRU_OFFSET
#define XTE_RXFL_OFFSET
#define XTE_RXFU_OFFSET
#define XTE_RXFCSERL_OFFSET
#define XTE_RXFCSERU_OFFSET
#define XTE_RXBCSTFL_OFFSET
#define XTE_RXBCSTFU_OFFSET
#define XTE_RXMCSTFL_OFFSET
#define XTE_RXMCSTFU_OFFSET
#define XTE_RXCTRFL_OFFSET
#define XTE_RXCTRFU_OFFSET
#define XTE_RXLTERL_OFFSET
#define XTE_RXLTERU_OFFSET
#define XTE_RXVLANFL_OFFSET
#define XTE_RXVLANFU_OFFSET
#define XTE_RXPFL_OFFSET
#define XTE_RXPFU_OFFSET
#define XTE_RXUOPFL_OFFSET
#define XTE_RXUOPFU_OFFSET
#define XTE_TXFL_OFFSET
#define XTE_TXFU_OFFSET
#define XTE_TXBCSTFL_OFFSET
#define XTE_TXBCSTFU_OFFSET
#define XTE_TXMCSTFL_OFFSET
#define XTE_TXMCSTFU_OFFSET
#define XTE_TXUNDRERL_OFFSET
#define XTE_TXUNDRERU_OFFSET
#define XTE_TXCTRFL_OFFSET
#define XTE_TXCTRFU_OFFSET
#define XTE_TXVLANFL_OFFSET
#define XTE_TXVLANFU_OFFSET
#define XTE_TXPFL_OFFSET
#define XTE_TXPFU_OFFSET

HARD_TEMAC Core Registers

These are registers defined within the device's hard core located in the processor block. They are accessed indirectly through the registers, MSW, LSW, and CTL.

Access to these registers should go through macros XLlTemac_ReadIndirectReg() and XLlTemac_WriteIndirectReg() to guarantee proper access.

#define XTE_RCW0_OFFSET
#define XTE_RCW1_OFFSET
#define XTE_TC_OFFSET
#define XTE_FCC_OFFSET
#define XTE_EMMC_OFFSET
#define XTE_PHYC_OFFSET
#define XTE_MC_OFFSET
#define XTE_UAW0_OFFSET
#define XTE_UAW1_OFFSET
#define XTE_MAW0_OFFSET
#define XTE_MAW1_OFFSET
#define XTE_AFM_OFFSET
#define XTE_TIS_OFFSET
#define XTE_TIE_OFFSET
#define XTE_MIIMWD_OFFSET
#define XTE_MIIMAI_OFFSET

Transmit VLAN Data Table

This offset defines an offset to table that has provisioned transmit VLAN data. It is stored in BRAM and will be used by hardware to provide transmit VLAN tag, strip, and translation.

#define XTE_TX_VLAN_DATA_OFFSET

Receive VLAN Data Table

This offset defines an offset to table that has provisioned receive VLAN data. It is stored in BRAM and will be used by hardware to provide receive VLAN tag, strip, and translation.

#define XTE_RX_VLAN_DATA_OFFSET

Extended Multicast Address Table

This offset defines an offset to table that has provisioned multicast addresses. It is stored in BRAM and will be used by hardware to provide first line of address matching when a multicast frame is reveived. It can minimize the use of CPU/software hence minimize performance impact.

#define XTE_MCAST_BRAM_OFFSET

Reset and Address Filter bits

These bits are associated with the XTE_RAF_OFFSET register.

#define XTE_RAF_HTRST_MASK
#define XTE_RAF_MCSTREJ_MASK
#define XTE_RAF_BCSTREJ_MASK
#define XTE_RAF_TXVTAGMODE_MASK
#define XTE_RAF_RXVTAGMODE_MASK
#define XTE_RAF_TXVSTRPMODE_MASK
#define XTE_RAF_RXVSTRPMODE_MASK
#define XTE_RAF_NEWFNCENBL_MASK
#define XTE_RAF_EMULTIFLTRENBL_MASK
#define XTE_RAF_TXVTAGMODE_SHIFT
#define XTE_RAF_RXVTAGMODE_SHIFT
#define XTE_RAF_TXVSTRPMODE_SHIFT
#define XTE_RAF_RXVSTRPMODE_SHIFT

Transmit Pause Frame Register (TPF)

#define XTE_TPF_TPFV_MASK

Transmit Inter-Frame Gap Adjustement Register (TFGP)

#define XTE_TFGP_IFGP_MASK

Interrupt bits

These bits are associated with the XTE_IS_OFFSET, XTE_IP_OFFSET, and XTE_IE_OFFSET registers.

#define XTE_INT_HARDACSCMPLT_MASK
#define XTE_INT_AUTONEG_MASK
#define XTE_INT_RC_MASK
#define XTE_INT_RXRJECT_MASK
#define XTE_INT_RXFIFOOVR_MASK
#define XTE_INT_TC_MASK
#define XTE_INT_RXDCM_LOCK_MASK
#define XTE_INT_MGT_LOCK_MASK
#define XTE_INT_ALL_MASK

Control Register (CTL)

#define XTE_CTL_WEN_MASK

TPID Register (TPID)

#define XTE_TPID_0_MASK
#define XTE_TPID_1_MASK

Ready Status, TEMAC Interrupt Status, TEMAC Interrupt Enable Registers

(RDY, TIS, TIE)

#define XTE_RSE_FABR_RR_MASK
#define XTE_RSE_MIIM_RR_MASK
#define XTE_RSE_MIIM_WR_MASK
#define XTE_RSE_AF_RR_MASK
#define XTE_RSE_AF_WR_MASK
#define XTE_RSE_CFG_RR_MASK
#define XTE_RSE_CFG_WR_MASK
#define XTE_RDY_HARD_ACS_RDY_MASK
#define XTE_RDY_ALL

Receive Configuration Word 1 (RCW1)

#define XTE_RCW1_RST_MASK
#define XTE_RCW1_JUM_MASK
#define XTE_RCW1_FCS_MASK
#define XTE_RCW1_RX_MASK
#define XTE_RCW1_VLAN_MASK
#define XTE_RCW1_HD_MASK
#define XTE_RCW1_LT_DIS_MASK
#define XTE_RCW1_PAUSEADDR_MASK

Transmitter Configuration (TC)

#define XTE_TC_RST_MASK
#define XTE_TC_JUM_MASK
#define XTE_TC_FCS_MASK
#define XTE_TC_TX_MASK
#define XTE_TC_VLAN_MASK
#define XTE_TC_HD_MASK
#define XTE_TC_IFG_MASK

Flow Control Configuration (FCC)

#define XTE_FCC_FCRX_MASK
#define XTE_FCC_FCTX_MASK

EMAC Configuration (EMMC)

#define XTE_EMMC_LINKSPEED_MASK
#define XTE_EMMC_RGMII_MASK
#define XTE_EMMC_SGMII_MASK
#define XTE_EMMC_GPCS_MASK
#define XTE_EMMC_HOST_MASK
#define XTE_EMMC_TX16BIT
#define XTE_EMMC_RX16BIT
#define XTE_EMMC_LINKSPD_10
#define XTE_EMMC_LINKSPD_100
#define XTE_EMMC_LINKSPD_1000

EMAC RGMII/SGMII Configuration (PHYC)

#define XTE_PHYC_SGMIILINKSPEED_MASK
#define XTE_PHYC_RGMIILINKSPEED_MASK
#define XTE_PHYC_RGMIIHD_MASK
#define XTE_PHYC_RGMIILINK_MASK
#define XTE_PHYC_RGLINKSPD_10
#define XTE_PHYC_RGLINKSPD_100
#define XTE_PHYC_RGLINKSPD_1000
#define XTE_PHYC_SGLINKSPD_10
#define XTE_PHYC_SGLINKSPD_100
#define XTE_PHYC_SGLINKSPD_1000

EMAC Management Configuration (MC)

#define XTE_MC_MDIOEN_MASK
#define XTE_MC_CLOCK_DIVIDE_MAX

EMAC Unicast Address Register Word 1 (UAW1)

#define XTE_UAW1_UNICASTADDR_MASK

EMAC Multicast Address Register Word 1 (MAW1)

#define XTE_MAW1_RNW_MASK
#define XTE_MAW1_ADDR_MASK
#define XTE_MAW1_MULTICADDR_MASK
#define XTE_MAW1_MATADDR_SHIFT_MASK

EMAC Address Filter Mode (AFM)

#define XTE_AFM_PM_MASK

Media Independent Interface Management (MIIM)

#define XTE_MIIM_REGAD_MASK
#define XTE_MIIM_PHYAD_MASK
#define XTE_MIIM_PHYAD_SHIFT

Checksum offload buffer descriptor extensions

#define XTE_BD_TX_CSBEGIN_OFFSET
#define XTE_BD_TX_CSINSERT_OFFSET
#define XTE_BD_TX_CSCNTRL_OFFSET
#define XTE_BD_TX_CSINIT_OFFSET
#define XTE_BD_RX_CSRAW_OFFSET

TX_CSCNTRL bit mask

#define XTE_BD_TX_CSCNTRL_CALC_MASK

Defines

#define XTE_RESET_HARD_DELAY_US
#define XTE_INT_RECV_ERROR_MASK
#define XLlTemac_ReadReg(BaseAddress, RegOffset)
#define XLlTemac_WriteReg(BaseAddress, RegOffset, Data)
#define XLlTemac_ReadIndirectReg(BaseAddress, RegOffset)
#define XLlTemac_WriteIndirectReg(BaseAddress, RegOffset, Data)


Define Documentation

#define XLlTemac_ReadIndirectReg BaseAddress,
RegOffset   ) 
 

XLlTemac_ReadIndirectReg returns the value read from the hard TEMAC register specified by RegOffset.

Parameters:
BaseAddress is the base address of the TEMAC channel.
RegOffset is the offset of the hard TEMAC register to be read.
Returns:
XLlTemac_ReadIndirectReg returns the 32-bit value of the register.
Note:
C-style signature: u32 XLlTemac_mReadIndirectReg(u32 BaseAddress, u32 RegOffset)

#define XLlTemac_ReadReg BaseAddress,
RegOffset   ) 
 

XLlTemac_ReadReg returns the value read from the register specified by RegOffset.

Parameters:
BaseAddress is the base address of the TEMAC channel.
RegOffset is the offset of the register to be read.
Returns:
XLlTemac_ReadReg returns the 32-bit value of the register.
Note:
C-style signature: u32 XLlTemac_mReadReg(u32 BaseAddress, u32 RegOffset)

#define XLlTemac_WriteIndirectReg BaseAddress,
RegOffset,
Data   ) 
 

XLlTemac_WriteIndirectReg, writes Data to the hard TEMAC register specified by RegOffset.

Parameters:
BaseAddress is the base address of the TEMAC channel.
RegOffset is the offset of the hard TEMAC register to be written.
Data is the 32-bit value to write to the register.
Returns:
N/A
Note:
C-style signature: void XLlTemac_WriteIndirectReg(u32 BaseAddress, u32 RegOffset, u32 Data)

#define XLlTemac_WriteReg BaseAddress,
RegOffset,
Data   ) 
 

XLlTemac_WriteReg, writes Data to the register specified by RegOffset.

Parameters:
BaseAddress is the base address of the TEMAC channel.
RegOffset is the offset of the register to be written.
Data is the 32-bit value to write to the register.
Returns:
N/A
Note:
C-style signature: void XLlTemac_mWriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

#define XTE_AFM_OFFSET
 

Address Filter (promiscuous) mode

#define XTE_AFM_PM_MASK
 

Promiscuous mode enable

#define XTE_BD_RX_CSRAW_OFFSET
 

Receive frame checksum calculation (16 bit word)

#define XTE_BD_TX_CSBEGIN_OFFSET
 

Byte offset where checksum should begin (16 bit word)

#define XTE_BD_TX_CSCNTRL_CALC_MASK
 

Enable/disable Tx checksum

#define XTE_BD_TX_CSCNTRL_OFFSET
 

Checksum offload control for transmit (16 bit word)

#define XTE_BD_TX_CSINIT_OFFSET
 

Seed value for checksum calculation (16 bit word)

#define XTE_BD_TX_CSINSERT_OFFSET
 

Offset where checksum should be inserted (16 bit word)

#define XTE_CTL_OFFSET
 

Control

#define XTE_CTL_WEN_MASK
 

Write Enable

#define XTE_EMMC_GPCS_MASK
 

1000BaseX mode enable

#define XTE_EMMC_HOST_MASK
 

Host interface enable

#define XTE_EMMC_LINKSPD_10
 

XTE_EMCFG_LINKSPD_MASK for 10 Mbit

#define XTE_EMMC_LINKSPD_100
 

XTE_EMCFG_LINKSPD_MASK for 100 Mbit

#define XTE_EMMC_LINKSPD_1000
 

XTE_EMCFG_LINKSPD_MASK for 1000 Mbit

#define XTE_EMMC_LINKSPEED_MASK
 

Link speed

#define XTE_EMMC_OFFSET
 

EMAC mode configuration

#define XTE_EMMC_RGMII_MASK
 

RGMII mode enable

#define XTE_EMMC_RX16BIT
 

16 bit Rx client enable

#define XTE_EMMC_SGMII_MASK
 

SGMII mode enable

#define XTE_EMMC_TX16BIT
 

16 bit Tx client enable

#define XTE_FCC_FCRX_MASK
 

Rx flow control enable

#define XTE_FCC_FCTX_MASK
 

Tx flow control enable

#define XTE_FCC_OFFSET
 

Flow control configuration

#define XTE_IE_OFFSET
 

Interrupt enable

#define XTE_IFGP_OFFSET
 

Transmit inter-frame gap adjustment

#define XTE_INT_ALL_MASK
 

All the ints

#define XTE_INT_AUTONEG_MASK
 

Auto negotiation complete

#define XTE_INT_HARDACSCMPLT_MASK
 

Hard register access complete

#define XTE_INT_MGT_LOCK_MASK
 

MGT clock Lock

#define XTE_INT_RC_MASK
 

Receive complete

#define XTE_INT_RECV_ERROR_MASK
 

INT bits that indicate receive errors

#define XTE_INT_RXDCM_LOCK_MASK
 

Rx Dcm Lock

#define XTE_INT_RXFIFOOVR_MASK
 

Receive fifo overrun

#define XTE_INT_RXRJECT_MASK
 

Receive frame rejected

#define XTE_INT_TC_MASK
 

Transmit complete

#define XTE_IP_OFFSET
 

Interrupt pending

#define XTE_IS_OFFSET
 

Interrupt status

#define XTE_LSW_OFFSET
 

Least significant word data

#define XTE_MAW0_OFFSET
 

Multicast address word 0

#define XTE_MAW1_ADDR_MASK
 

Multicast address table register address

#define XTE_MAW1_MATADDR_SHIFT_MASK
 

Number of bits to shift right to align with XTE_MAW1_CAMADDR_MASK

#define XTE_MAW1_MULTICADDR_MASK
 

Multicast address bits [47:32] Multicast address bits [31:0] are stored in register MAW0

#define XTE_MAW1_OFFSET
 

Multicast address word 1

#define XTE_MAW1_RNW_MASK
 

Multicast address table register read enable

#define XTE_MC_CLOCK_DIVIDE_MAX
 

Maximum MDIO divisor

#define XTE_MC_MDIOEN_MASK
 

MII management enable

#define XTE_MC_OFFSET
 

Management configuration

#define XTE_MCAST_BRAM_OFFSET
 

multicast table address

#define XTE_MIIM_PHYAD_MASK
 

MII Phy address (PHYAD)

#define XTE_MIIM_PHYAD_SHIFT
 

MII Shift bits for PHYAD

#define XTE_MIIM_REGAD_MASK
 

MII Phy register address (REGAD)

#define XTE_MIIMAI_OFFSET
 

MII management access initiate

#define XTE_MIIMWD_OFFSET
 

MII management write data

#define XTE_MSW_OFFSET
 

Most significant word data

#define XTE_PHYC_OFFSET
 

RGMII/SGMII configuration

#define XTE_PHYC_RGLINKSPD_10
 

XTE_GMIC_RGLINKSPD_MASK for 10 Mbit

#define XTE_PHYC_RGLINKSPD_100
 

XTE_GMIC_RGLINKSPD_MASK for 100 Mbit

#define XTE_PHYC_RGLINKSPD_1000
 

XTE_GMIC_RGLINKSPD_MASK for 1000 Mbit

#define XTE_PHYC_RGMIIHD_MASK
 

RGMII Half-duplex mode

#define XTE_PHYC_RGMIILINK_MASK
 

RGMII link status

#define XTE_PHYC_RGMIILINKSPEED_MASK
 

RGMII link speed

#define XTE_PHYC_SGLINKSPD_10
 

XTE_SGMIC_RGLINKSPD_MASK for 10 Mbit

#define XTE_PHYC_SGLINKSPD_100
 

XTE_SGMIC_RGLINKSPD_MASK for 100 Mbit

#define XTE_PHYC_SGLINKSPD_1000
 

XTE_SGMIC_RGLINKSPD_MASK for 1000 Mbit

#define XTE_PHYC_SGMIILINKSPEED_MASK
 

SGMII link speed

#define XTE_RAF_BCSTREJ_MASK
 

Reject receive broadcast destination address

#define XTE_RAF_EMULTIFLTRENBL_MASK
 

Exteneded Multicast Filtering mode

#define XTE_RAF_HTRST_MASK
 

Hard TEMAC Reset

#define XTE_RAF_MCSTREJ_MASK
 

Reject receive multicast destination address

#define XTE_RAF_NEWFNCENBL_MASK
 

New function mode

#define XTE_RAF_OFFSET
 

Reset and address filter

#define XTE_RAF_RXVSTRPMODE_MASK
 

Rx VLAN STRIP mode

#define XTE_RAF_RXVSTRPMODE_SHIFT
 

Rx Strip mode shift bits

#define XTE_RAF_RXVTAGMODE_MASK
 

Rx VLAN TAG mode

#define XTE_RAF_RXVTAGMODE_SHIFT
 

Rx Tag mode shift bits

#define XTE_RAF_TXVSTRPMODE_MASK
 

Tx VLAN STRIP mode

#define XTE_RAF_TXVSTRPMODE_SHIFT
 

Tx strip mode shift bits

#define XTE_RAF_TXVTAGMODE_MASK
 

Tx VLAN TAG mode

#define XTE_RAF_TXVTAGMODE_SHIFT
 

Tx Tag mode shift bits

#define XTE_RCW0_OFFSET
 

Rx configuration word 0

#define XTE_RCW1_FCS_MASK
 

In-Band FCS enable (FCS not stripped)

#define XTE_RCW1_HD_MASK
 

Half duplex mode

#define XTE_RCW1_JUM_MASK
 

Jumbo frame enable

#define XTE_RCW1_LT_DIS_MASK
 

Length/type field valid check disable

#define XTE_RCW1_OFFSET
 

Rx configuration word 1

#define XTE_RCW1_PAUSEADDR_MASK
 

Pause frame source address bits [47:32]. Bits [31:0] are stored in register RCW0

#define XTE_RCW1_RST_MASK
 

Reset

#define XTE_RCW1_RX_MASK
 

Receiver enable

#define XTE_RCW1_VLAN_MASK
 

VLAN frame enable

#define XTE_RDY_HARD_ACS_RDY_MASK
 

Hard register access ready

#define XTE_RDY_OFFSET
 

Ready status

#define XTE_RESET_HARD_DELAY_US
 

Us to delay for hard core reset

#define XTE_RSE_AF_RR_MASK
 

Address filter read ready

#define XTE_RSE_AF_WR_MASK
 

Address filter write ready

#define XTE_RSE_CFG_RR_MASK
 

Configuration register read ready

#define XTE_RSE_CFG_WR_MASK
 

Configuration register write ready

#define XTE_RSE_FABR_RR_MASK
 

Fabric read ready

#define XTE_RSE_MIIM_RR_MASK
 

MII management read ready

#define XTE_RSE_MIIM_WR_MASK
 

MII management write ready

#define XTE_RTAG_OFFSET
 

Rx VLAN TAG

#define XTE_RX1024BL_OFFSET
 

Frames count of 1024-MAX bytes frames received, least significant word

#define XTE_RX1024BU_OFFSET
 

Frames count of 1024-MAX bytes frames received, most significant word

#define XTE_RX128B255L_OFFSET
 

Frames count of 128-255 bytes frames received, least significant word

#define XTE_RX128B255U_OFFSET
 

Frames count of 128-255 bytes frames received, most significant word

#define XTE_RX256B511L_OFFSET
 

Frames count of 256-511 bytes frames received, least significant word

#define XTE_RX256B511U_OFFSET
 

Frames count of 256-511 bytes frames received, most significant word

#define XTE_RX512B1023L_OFFSET
 

Frames count of 512-1023 bytes frames received, least significant word

#define XTE_RX512B1023U_OFFSET
 

Frames count of 512-1023 bytes frames received, most significant word

#define XTE_RX64BL_OFFSET
 

Frames count of 64 bytes frames received, least significant word

#define XTE_RX64BU_OFFSET
 

Frames count of 64 bytes frames received, most significant word

#define XTE_RX65B127L_OFFSET
 

Frames count of 65-127 bytes frames received, least significant word

#define XTE_RX65B127U_OFFSET
 

Frames count of 65-127 bytes frames received, most significant word

#define XTE_RX_VLAN_DATA_OFFSET
 

TX VLAN data table address

#define XTE_RXBCSTFL_OFFSET
 

Frames count of broadcast frames received, least significant word

#define XTE_RXBCSTFU_OFFSET
 

Frames count of broadcast frames received, most significant word

#define XTE_RXBL_OFFSET
 

Bytes count of received frames, least significant word

#define XTE_RXBU_OFFSET
 

Bytes count of received frames, most significant word

#define XTE_RXCTRFL_OFFSET
 

Frames count of control frames received, least significant word

#define XTE_RXCTRFU_OFFSET
 

Frames count of control frames received, most significant word

#define XTE_RXFCSERL_OFFSET
 

Frames count of frames received FCS error and at least 64 bytes, least significant word

#define XTE_RXFCSERU_OFFSET
 

Frames count of frames received FCS error and at least 64 bytes, most significant word

#define XTE_RXFL_OFFSET
 

Frames count of frames received OK, least significant word

#define XTE_RXFRAGL_OFFSET
 

Frames count of undersized(less than 64 bytes) and bad FCS frames received, least significant word

#define XTE_RXFRAGU_OFFSET
 

Frames count of undersized(less than 64 bytes) and bad FCS frames received, most significant word

#define XTE_RXFU_OFFSET
 

Frames count of frames received OK, most significant word

#define XTE_RXLTERL_OFFSET
 

Frames count of frames received with length error, least significant word

#define XTE_RXLTERU_OFFSET
 

Frames count of frames received with length error, most significant word

#define XTE_RXMCSTFL_OFFSET
 

Frames count of multicast frames received, least significant word

#define XTE_RXMCSTFU_OFFSET
 

Frames count of multicast frames received, most significant word

#define XTE_RXOVRL_OFFSET
 

Frames count of oversize frames received, least significant word

#define XTE_RXOVRU_OFFSET
 

Frames count of oversize frames received, most significant word

#define XTE_RXPFL_OFFSET
 

Frames count of pause frames received, least significant word

#define XTE_RXPFU_OFFSET
 

Frames count of pause frames received, most significant word

#define XTE_RXUNDRL_OFFSET
 

Frames count of undersize(less than 64 bytes) frames received, least significant word

#define XTE_RXUNDRU_OFFSET
 

Frames count of undersize(less than 64 bytes) frames received, most significant word

#define XTE_RXUOPFL_OFFSET
 

Frames count of control frames received with unsupported opcode, least significant word

#define XTE_RXUOPFU_OFFSET
 

Frames count of control frames received with unsupported opcode, most significant word

#define XTE_RXVLANFL_OFFSET
 

Frames count of VLAN tagged frames received, least significant word

#define XTE_RXVLANFU_OFFSET
 

Frames count of VLAN tagged frames received, most significant word

#define XTE_TC_FCS_MASK
 

In-Band FCS enable (FCS not generated)

#define XTE_TC_HD_MASK
 

Half duplex mode

#define XTE_TC_IFG_MASK
 

Inter-frame gap adjustment enable

#define XTE_TC_JUM_MASK
 

Jumbo frame enable

#define XTE_TC_OFFSET
 

Tx configuration

#define XTE_TC_RST_MASK
 

reset

#define XTE_TC_TX_MASK
 

Transmitter enable

#define XTE_TC_VLAN_MASK
 

VLAN frame enable

#define XTE_TFGP_IFGP_MASK
 

Transmit inter-frame gap adjustment value

#define XTE_TIE_OFFSET
 

Interrupt enable

#define XTE_TIS_OFFSET
 

Interrupt status

#define XTE_TPF_OFFSET
 

Transmit pause frame

#define XTE_TPF_TPFV_MASK
 

Tx pause frame value

#define XTE_TPID0_OFFSET
 

TPID0 register

#define XTE_TPID1_OFFSET
 

TPID1 register

#define XTE_TPID_0_MASK
 

TPID 0

#define XTE_TPID_1_MASK
 

TPID 1

#define XTE_TTAG_OFFSET
 

Tx VLAN TAG

#define XTE_TX1024L_OFFSET
 

Frames count of 1024-MAX bytes frames transmitted, least significant word

#define XTE_TX1024U_OFFSET
 

Frames count of 1024-MAX bytes frames transmitted, most significant word

#define XTE_TX128B255L_OFFSET
 

Frames count of 128-255 bytes frames transmitted, least significant word

#define XTE_TX128B255U_OFFSET
 

Frames count of 128-255 bytes frames transmitted, most significant word

#define XTE_TX256B511L_OFFSET
 

Frames count of 256-511 bytes frames transmittereceived, least significant word

#define XTE_TX256B511U_OFFSET
 

Frames count of 256-511 bytes frames transmitted, most significant word

#define XTE_TX512B1023L_OFFSET
 

Frames count of 512-1023 bytes frames transmitted, least significant word

#define XTE_TX512B1023U_OFFSET
 

Frames count of 512-1023 bytes frames transmitted, most significant word

#define XTE_TX64BL_OFFSET
 

Frames count of 64 bytes frames transmitted, least significant word

#define XTE_TX64BU_OFFSET
 

Frames count of 64 bytes frames transmitted, most significant word

#define XTE_TX65B127L_OFFSET
 

Frames count of 65-127 bytes frames transmitted, least significant word

#define XTE_TX65B127U_OFFSET
 

Frames count of 65-127 bytes frames transmitted, most significant word

#define XTE_TX_VLAN_DATA_OFFSET
 

TX VLAN data table address

#define XTE_TXBCSTFL_OFFSET
 

Frames count of broadcast frames transmitted, least significant word

#define XTE_TXBCSTFU_OFFSET
 

Frames count of broadcast frames transmitted, most significant word

#define XTE_TXBL_OFFSET
 

Bytes count of transmitted frames, least significant word

#define XTE_TXBU_OFFSET
 

Bytes count of transmitted frames, most significant word

#define XTE_TXCTRFL_OFFSET
 

Frames count of control frames transmitted, least significant word

#define XTE_TXCTRFU_OFFSET
 

Frames count of control frames transmitted, most significant word

#define XTE_TXFL_OFFSET
 

Frames count of frames transmitted OK, least significant word

#define XTE_TXFU_OFFSET
 

Frames count of frames transmitted OK, most significant word

#define XTE_TXMCSTFL_OFFSET
 

Frames count of multicast frames transmitted, least significant word

#define XTE_TXMCSTFU_OFFSET
 

Frames count of multicast frames transmitted, most significant word

#define XTE_TXOVRL_OFFSET
 

Frames count of oversize frames transmitted, least significant word

#define XTE_TXOVRU_OFFSET
 

Frames count of oversize frames transmitted, most significant word

#define XTE_TXPFL_OFFSET
 

Frames count of pause frames transmitted, least significant word

#define XTE_TXPFU_OFFSET
 

Frames count of pause frames transmitted, most significant word

#define XTE_TXUNDRERL_OFFSET
 

Frames count of frames transmitted underrun error, least significant word

#define XTE_TXUNDRERU_OFFSET
 

Frames count of frames transmitted underrun error, most significant word

#define XTE_TXVLANFL_OFFSET
 

Frames count of VLAN tagged frames transmitted, least significant word

#define XTE_TXVLANFU_OFFSET
 

Frames count of VLAN tagged frames transmitted, most significant word

#define XTE_UAW0_OFFSET
 

Unicast address word 0

#define XTE_UAW1_OFFSET
 

Unicast address word 1

#define XTE_UAW1_UNICASTADDR_MASK
 

Station address bits [47:32] Station address bits [31:0] are stored in register UAW0

#define XTE_UAWL_OFFSET
 

Unicast address, extended/new multicast mode

#define XTE_UAWU_OFFSET
 

Unicast address, extended/new multicast mode