Name |
Value |
C_FAMILY |
virtex5 |
C_MPMC_BASEADDR |
0x20000000 |
C_MPMC_CTRL_BASEADDR |
0xFFFFFFFF |
C_MPMC_CTRL_HIGHADDR |
0x00000000 |
C_MPMC_HIGHADDR |
0x27FFFFFF |
C_MPMC_SW_BASEADDR |
0xFFFFFFFF |
C_MPMC_SW_HIGHADDR |
0x00000000 |
C_PIM0_BASEADDR |
0xFFFFFFFF |
C_PIM0_HIGHADDR |
0x00000000 |
C_PIM1_BASEADDR |
0xFFFFFFFF |
C_PIM1_HIGHADDR |
0x00000000 |
C_PIM2_BASEADDR |
0xFFFFFFFF |
C_PIM2_HIGHADDR |
0x00000000 |
C_PIM3_BASEADDR |
0xFFFFFFFF |
C_PIM3_HIGHADDR |
0x00000000 |
C_PIM4_BASEADDR |
0xFFFFFFFF |
C_PIM4_HIGHADDR |
0x00000000 |
C_PIM5_BASEADDR |
0xFFFFFFFF |
C_PIM5_HIGHADDR |
0x00000000 |
C_PIM6_BASEADDR |
0xFFFFFFFF |
C_PIM6_HIGHADDR |
0x00000000 |
C_PIM7_BASEADDR |
0xFFFFFFFF |
C_PIM7_HIGHADDR |
0x00000000 |
C_SDMA_CTRL0_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL0_HIGHADDR |
0x00000000 |
C_SDMA_CTRL1_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL1_HIGHADDR |
0x00000000 |
C_SDMA_CTRL2_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL2_HIGHADDR |
0x00000000 |
C_SDMA_CTRL3_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL3_HIGHADDR |
0x00000000 |
C_SDMA_CTRL4_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL4_HIGHADDR |
0x00000000 |
C_SDMA_CTRL5_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL5_HIGHADDR |
0x00000000 |
C_SDMA_CTRL6_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL6_HIGHADDR |
0x00000000 |
C_SDMA_CTRL7_BASEADDR |
0xFFFFFFFF |
C_SDMA_CTRL7_HIGHADDR |
0x00000000 |
C_SDMA_CTRL_BASEADDR |
0x8ADF0000 |
C_SDMA_CTRL_HIGHADDR |
0x8ADFFFFF |
C_ALL_PIMS_SHARE_ADDRESSES |
1 |
C_ARB0_ALGO |
ROUND_ROBIN |
C_ARB0_NUM_SLOTS |
8 |
C_ARB0_SLOT0 |
01234567 |
C_ARB0_SLOT1 |
12345670 |
C_ARB0_SLOT10 |
23456701 |
C_ARB0_SLOT11 |
34567012 |
C_ARB0_SLOT12 |
45670123 |
C_ARB0_SLOT13 |
56701234 |
C_ARB0_SLOT14 |
67012345 |
C_ARB0_SLOT15 |
70123456 |
C_ARB0_SLOT2 |
23456701 |
C_ARB0_SLOT3 |
34567012 |
C_ARB0_SLOT4 |
45670123 |
C_ARB0_SLOT5 |
56701234 |
C_ARB0_SLOT6 |
67012345 |
C_ARB0_SLOT7 |
70123456 |
C_ARB0_SLOT8 |
01234567 |
C_ARB0_SLOT9 |
12345670 |
C_ARB_BRAM_INIT_00 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000 |
C_ARB_BRAM_INIT_01 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_ARB_BRAM_INIT_02 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000 |
C_ARB_BRAM_INIT_03 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_ARB_BRAM_INIT_04 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000 |
C_ARB_BRAM_INIT_05 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_ARB_BRAM_INIT_06 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000 |
C_ARB_BRAM_INIT_07 |
0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111 |
C_ARB_PIPELINE |
1 |
C_ARB_USE_DEFAULT |
0 |
C_B16_REPEAT_CNT |
0 |
C_B32_REPEAT_CNT |
0 |
C_B64_REPEAT_CNT |
0 |
C_BASEADDR_CTRL0 |
0x000 |
C_BASEADDR_CTRL1 |
0x00E |
C_BASEADDR_CTRL10 |
0x09E |
C_BASEADDR_CTRL11 |
0x0A6 |
C_BASEADDR_CTRL12 |
0x0AE |
C_BASEADDR_CTRL13 |
0x0B6 |
C_BASEADDR_CTRL14 |
0x0BE |
C_BASEADDR_CTRL15 |
0x0D1 |
C_BASEADDR_CTRL2 |
0x018 |
C_BASEADDR_CTRL3 |
0x026 |
C_BASEADDR_CTRL4 |
0x030 |
C_BASEADDR_CTRL5 |
0x03E |
C_BASEADDR_CTRL6 |
0x048 |
C_BASEADDR_CTRL7 |
0x05C |
C_BASEADDR_CTRL8 |
0x06B |
C_BASEADDR_CTRL9 |
0x087 |
C_CTRL_AP_COL_CNT_ENABLE_INDEX |
0 |
C_CTRL_AP_COL_CNT_LOAD_INDEX |
0 |
C_CTRL_AP_COL_DELAY |
0 |
C_CTRL_AP_OTF_ADDR12_INDEX |
0 |
C_CTRL_AP_PIPELINE1_CE_DELAY |
0 |
C_CTRL_AP_PI_ADDR_CE_DELAY |
0 |
C_CTRL_AP_PORT_SELECT_DELAY |
0 |
C_CTRL_AP_PRECHARGE_ADDR10_INDEX |
0 |
C_CTRL_AP_ROW_COL_SEL_INDEX |
0 |
C_CTRL_ARB_RDMODWR_DELAY |
0 |
C_CTRL_BRAM_INITP_00 |
0x1111111111110001111110111111111111111001111110111111111111111001 |
C_CTRL_BRAM_INITP_01 |
0x1110000000000000000011111111111111111111111111000000000111111011 |
C_CTRL_BRAM_INITP_02 |
0x1110000000000000000000000000000000011111111111111111111111111111 |
C_CTRL_BRAM_INITP_03 |
0x0000000000000000000000000000000000000000000000001111111111111111 |
C_CTRL_BRAM_INITP_04 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INITP_05 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INITP_06 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INITP_07 |
0x0000000000000000000000000000000000000000000000000000000000000000 |
C_CTRL_BRAM_INIT_00 |
0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_INIT_01 |
0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD |
C_CTRL_BRAM_INIT_02 |
0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC |
C_CTRL_BRAM_INIT_03 |
0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_INIT_04 |
0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD |
C_CTRL_BRAM_INIT_05 |
0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC |
C_CTRL_BRAM_INIT_06 |
0x000002FC000002FC000002FC0000093C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_INIT_07 |
0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD |
C_CTRL_BRAM_INIT_08 |
0x000002FC000002FC000002FC000042E8000002FC000006FD000016F4000082FC |
C_CTRL_BRAM_INIT_09 |
0x000029240000093C000029240000093C000019240000803C000082FC000082F8 |
C_CTRL_BRAM_INIT_0A |
0x000002FC000002FD000002FC000002FC000002FC0000093C000029240000093C |
C_CTRL_BRAM_INIT_0B |
0x000016F4000082FC000082FC000082F8000002FC000002FC000002FC000042E8 |
C_CTRL_BRAM_INIT_0C |
0x000042E8000006FC000026F5000006FC000026F4000006FC000026F4000006FC |
C_CTRL_BRAM_INIT_0D |
0x0000093C000019240000803C000082FC000082F8000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_0E |
0x0000093C000029240000093C000029240000093C000029240000093C00002924 |
C_CTRL_BRAM_INIT_0F |
0x000002FC000002FC0000093C000029240000093C000029240000093C00002924 |
C_CTRL_BRAM_INIT_10 |
0x000082F8000002FC000002FC000002FC000042E8000002FC000002FD000002FC |
C_CTRL_BRAM_INIT_11 |
0x000006FC000026F4000006FC000026F4000006FC000016F4000082FC000082FC |
C_CTRL_BRAM_INIT_12 |
0x000006FC000026F4000006FC000026F4000006FC000026F4000006FC000026F4 |
C_CTRL_BRAM_INIT_13 |
0x000002FC000002FC000002FC000002FC000002FC000042E8000006FC000026F5 |
C_CTRL_BRAM_INIT_14 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_15 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_16 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_17 |
0x000002FC000042E8000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_18 |
0x000002FC000002FC000002FC000002FC000002FC000002F0000002FC000002FC |
C_CTRL_BRAM_INIT_19 |
0x000002FC000002FC000002FC000002FC000002FD000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1A |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1B |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1C |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1D |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1E |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_1F |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_20 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_21 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_22 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_23 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_24 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_25 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_26 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_27 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_28 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_29 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2A |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2B |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2C |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2D |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2E |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_2F |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_30 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_31 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_32 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_33 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_34 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_35 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_36 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_37 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_38 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_39 |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3A |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3B |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3C |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3D |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3E |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_INIT_3F |
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC |
C_CTRL_BRAM_SRVAL |
0x0000002FC |
C_CTRL_COMPLETE_INDEX |
0 |
C_CTRL_DFI_CAS_N_0_INDEX |
0 |
C_CTRL_DFI_CAS_N_1_INDEX |
0 |
C_CTRL_DFI_RAS_N_0_INDEX |
0 |
C_CTRL_DFI_RAS_N_1_INDEX |
0 |
C_CTRL_DFI_RDDATA_EN_INDEX |
0 |
C_CTRL_DFI_WE_N_0_INDEX |
0 |
C_CTRL_DFI_WE_N_1_INDEX |
0 |
C_CTRL_DFI_WRDATA_EN_INDEX |
0 |
C_CTRL_DP_LOAD_RDWDADDR_DELAY |
0 |
C_CTRL_DP_RDFIFO_PUSH_INDEX |
0 |
C_CTRL_DP_RDFIFO_WHICHPORT_DELAY |
0 |
C_CTRL_DP_SIZE_DELAY |
0 |
C_CTRL_DP_WRFIFO_POP_INDEX |
0 |
C_CTRL_DP_WRFIFO_WHICHPORT_DELAY |
0 |
C_CTRL_IS_WRITE_INDEX |
0 |
C_CTRL_PHYIF_CAS_N_INDEX |
0 |
C_CTRL_PHYIF_DQS_O_INDEX |
0 |
C_CTRL_PHYIF_DUMMYREADSTART_DELAY |
0 |
C_CTRL_PHYIF_FORCE_DM_INDEX |
0 |
C_CTRL_PHYIF_RAS_N_INDEX |
0 |
C_CTRL_PHYIF_WE_N_INDEX |
0 |
C_CTRL_Q0_DELAY |
0 |
C_CTRL_Q10_DELAY |
0 |
C_CTRL_Q11_DELAY |
0 |
C_CTRL_Q12_DELAY |
0 |
C_CTRL_Q13_DELAY |
0 |
C_CTRL_Q14_DELAY |
0 |
C_CTRL_Q15_DELAY |
0 |
C_CTRL_Q16_DELAY |
0 |
C_CTRL_Q17_DELAY |
0 |
C_CTRL_Q18_DELAY |
0 |
C_CTRL_Q19_DELAY |
0 |
C_CTRL_Q1_DELAY |
0 |
C_CTRL_Q20_DELAY |
0 |
C_CTRL_Q21_DELAY |
0 |
C_CTRL_Q22_DELAY |
0 |
C_CTRL_Q23_DELAY |
0 |
C_CTRL_Q24_DELAY |
0 |
C_CTRL_Q25_DELAY |
0 |
C_CTRL_Q26_DELAY |
0 |
C_CTRL_Q27_DELAY |
0 |
C_CTRL_Q28_DELAY |
0 |
C_CTRL_Q29_DELAY |
0 |
C_CTRL_Q2_DELAY |
0 |
C_CTRL_Q30_DELAY |
0 |
C_CTRL_Q31_DELAY |
0 |
C_CTRL_Q32_DELAY |
0 |
C_CTRL_Q33_DELAY |
0 |
C_CTRL_Q34_DELAY |
0 |
C_CTRL_Q35_DELAY |
0 |
C_CTRL_Q3_DELAY |
0 |
C_CTRL_Q4_DELAY |
0 |
C_CTRL_Q5_DELAY |
0 |
C_CTRL_Q6_DELAY |
0 |
C_CTRL_Q7_DELAY |
0 |
C_CTRL_Q8_DELAY |
0 |
C_CTRL_Q9_DELAY |
0 |
C_CTRL_REPEAT4_INDEX |
0 |
C_CTRL_RMW_INDEX |
0 |
C_CTRL_SKIP_0_INDEX |
0 |
C_CTRL_SKIP_1_INDEX |
0 |
C_CTRL_SKIP_2_INDEX |
0 |
C_DDR2_DQSN_ENABLE |
1 |
C_DEBUG_REG_ENABLE |
0 |
C_DEVICE |
5vlx50t |
C_ECC_DATA_WIDTH |
0 |
C_ECC_DEC_THRESHOLD |
1 |
C_ECC_DEFAULT_ON |
1 |
C_ECC_DM_WIDTH |
0 |
C_ECC_DQS_WIDTH |
0 |
C_ECC_PEC_THRESHOLD |
1 |
C_ECC_SEC_THRESHOLD |
1 |
C_HIGHADDR_CTRL0 |
0x00D |
C_HIGHADDR_CTRL1 |
0x017 |
C_HIGHADDR_CTRL10 |
0x0A5 |
C_HIGHADDR_CTRL11 |
0x0AD |
C_HIGHADDR_CTRL12 |
0x0B5 |
C_HIGHADDR_CTRL13 |
0x0BD |
C_HIGHADDR_CTRL14 |
0x0D0 |
C_HIGHADDR_CTRL15 |
0x0D8 |
C_HIGHADDR_CTRL2 |
0x025 |
C_HIGHADDR_CTRL3 |
0x02F |
C_HIGHADDR_CTRL4 |
0x03D |
C_HIGHADDR_CTRL5 |
0x047 |
C_HIGHADDR_CTRL6 |
0x05B |
C_HIGHADDR_CTRL7 |
0x06A |
C_HIGHADDR_CTRL8 |
0x086 |
C_HIGHADDR_CTRL9 |
0x09D |
C_IDELAYCTRL_LOC |
NOT_SET |
C_IDELAY_CLK_FREQ |
DEFAULT |
C_INCLUDE_ECC_SUPPORT |
0 |
C_INCLUDE_ECC_TEST |
0 |
C_IODELAY_GRP |
NOT_SET |
C_MAX_REQ_ALLOWED |
1 |
C_MCB_DQ0_TAP_DELAY_VAL |
0 |
C_MCB_DQ10_TAP_DELAY_VAL |
0 |
C_MCB_DQ11_TAP_DELAY_VAL |
0 |
C_MCB_DQ12_TAP_DELAY_VAL |
0 |
C_MCB_DQ13_TAP_DELAY_VAL |
0 |
C_MCB_DQ14_TAP_DELAY_VAL |
0 |
C_MCB_DQ15_TAP_DELAY_VAL |
0 |
C_MCB_DQ1_TAP_DELAY_VAL |
0 |
C_MCB_DQ2_TAP_DELAY_VAL |
0 |
C_MCB_DQ3_TAP_DELAY_VAL |
0 |
C_MCB_DQ4_TAP_DELAY_VAL |
0 |
C_MCB_DQ5_TAP_DELAY_VAL |
0 |
C_MCB_DQ6_TAP_DELAY_VAL |
0 |
C_MCB_DQ7_TAP_DELAY_VAL |
0 |
C_MCB_DQ8_TAP_DELAY_VAL |
0 |
C_MCB_DQ9_TAP_DELAY_VAL |
0 |
C_MCB_LDQSN_TAP_DELAY_VAL |
0 |
C_MCB_LDQSP_TAP_DELAY_VAL |
0 |
C_MCB_LOC |
NOT_SET |
C_MCB_UDQSN_TAP_DELAY_VAL |
0 |
C_MCB_UDQSP_TAP_DELAY_VAL |
0 |
C_MCB_USE_EXTERNAL_BUFPLL |
0 |
C_MEM_ADDR_ORDER |
BANK_ROW_COLUMN |
C_MEM_ADDR_WIDTH |
13 |
C_MEM_AUTO_SR |
ENABLED |
C_MEM_BANKADDR_WIDTH |
2 |
C_MEM_BITS_DATA_PER_DQS |
8 |
C_MEM_CALIBRATION_BYPASS |
NO |
C_MEM_CALIBRATION_DELAY |
HALF |
C_MEM_CALIBRATION_MODE |
1 |
C_MEM_CALIBRATION_SOFT_IP |
FALSE |
C_MEM_CAL_WIDTH |
DEFAULT |
C_MEM_CAS_LATENCY |
3 |
C_MEM_CAS_WR_LATENCY |
5 |
C_MEM_CE_WIDTH |
1 |
C_MEM_CHECK_MAX_INDELAY |
0 |
C_MEM_CHECK_MAX_TAP_REG |
0 |
C_MEM_CLK_WIDTH |
2 |
C_MEM_CS_N_WIDTH |
1 |
C_MEM_DATA_WIDTH |
32 |
C_MEM_DM_WIDTH |
4 |
C_MEM_DQS_IO_COL |
0x000000000000000000 |
C_MEM_DQS_LOC_COL0 |
0x000000000000000000000000000000000000 |
C_MEM_DQS_LOC_COL1 |
0x000000000000000000000000000000000000 |
C_MEM_DQS_LOC_COL2 |
0x000000000000000000000000000000000000 |
C_MEM_DQS_LOC_COL3 |
0x000000000000000000000000000000000000 |
C_MEM_DQS_WIDTH |
4 |
C_MEM_DQ_IO_MS |
0x000000000000000000 |
C_MEM_DYNAMIC_WRITE_ODT |
OFF |
C_MEM_HIGH_TEMP_SR |
NORMAL |
C_MEM_IBUF_LPWR_MODE |
DEFAULT |
C_MEM_INCDEC_THRESHOLD |
0x02 |
C_MEM_IODELAY_HP_MODE |
DEFAULT |
C_MEM_NDQS_COL0 |
0 |
C_MEM_NDQS_COL1 |
0 |
C_MEM_NDQS_COL2 |
0 |
C_MEM_NDQS_COL3 |
0 |
C_MEM_NUM_DIMMS |
1 |
C_MEM_NUM_RANKS |
1 |
C_MEM_OCB_MONITOR |
DEFAULT |
C_MEM_ODT_TYPE |
0 |
C_MEM_ODT_WIDTH |
1 |
C_MEM_PARTNO |
MT47H32M16-5E |
C_MEM_PART_CAS_A |
0 |
C_MEM_PART_CAS_A_FMAX |
0 |
C_MEM_PART_CAS_B |
0 |
C_MEM_PART_CAS_B_FMAX |
0 |
C_MEM_PART_CAS_C |
0 |
C_MEM_PART_CAS_C_FMAX |
0 |
C_MEM_PART_CAS_D |
0 |
C_MEM_PART_CAS_D_FMAX |
0 |
C_MEM_PART_DATA_DEPTH |
16 |
C_MEM_PART_DATA_WIDTH |
8 |
C_MEM_PART_NUM_BANK_BITS |
2 |
C_MEM_PART_NUM_COL_BITS |
9 |
C_MEM_PART_NUM_ROW_BITS |
13 |
C_MEM_PART_TAL |
0 |
C_MEM_PART_TCCD |
0 |
C_MEM_PART_TDQSS |
1 |
C_MEM_PART_TMRD |
4 |
C_MEM_PART_TRAS |
0 |
C_MEM_PART_TRASMAX |
0 |
C_MEM_PART_TRC |
0 |
C_MEM_PART_TRCD |
0 |
C_MEM_PART_TREFI |
0 |
C_MEM_PART_TRFC |
0 |
C_MEM_PART_TRP |
0 |
C_MEM_PART_TRRD |
0 |
C_MEM_PART_TRTP |
7500 |
C_MEM_PART_TWR |
0 |
C_MEM_PART_TWTR |
0 |
C_MEM_PART_TZQCS |
64 |
C_MEM_PART_TZQINIT |
512 |
C_MEM_PA_SR |
0 |
C_MEM_PHASE_DETECT |
DEFAULT |
C_MEM_REDUCED_DRV |
0 |
C_MEM_REG_DIMM |
0 |
C_MEM_SIM_CAL_OPTION |
DEFAULT |
C_MEM_SIM_INIT_OPTION |
DEFAULT |
C_MEM_SKIP_DYNAMIC_CAL |
1 |
C_MEM_SKIP_DYN_IN_TERM |
1 |
C_MEM_SKIP_IN_TERM_CAL |
1 |
C_MEM_TYPE |
DDR2 |
C_MEM_TZQINIT_MAXCNT |
512 |
C_MEM_WRLVL |
1 |
C_MMCM_EXT_LOC |
NOT_SET |
C_MMCM_INT_LOC |
NOT_SET |
C_MPMC_CLK0_PERIOD_PS |
1 |
C_MPMC_CLK_MEM_2X_PERIOD_PS |
1250 |
C_MPMC_CLK_MEM_PERIOD_PS |
1 |
C_MPMC_CLK_WR_I0_PHASE |
0 |
C_MPMC_CLK_WR_I1_PHASE |
0 |
C_MPMC_CLK_WR_O0_PHASE |
0 |
C_MPMC_CLK_WR_O1_PHASE |
0 |
C_MPMC_CTRL_AWIDTH |
32 |
C_MPMC_CTRL_DWIDTH |
64 |
C_MPMC_CTRL_MID_WIDTH |
1 |
C_MPMC_CTRL_NATIVE_DWIDTH |
32 |
C_MPMC_CTRL_NUM_MASTERS |
1 |
C_MPMC_CTRL_P2P |
1 |
C_MPMC_CTRL_SMALLEST_MASTER |
32 |
C_MPMC_CTRL_SUPPORT_BURSTS |
0 |
C_NCK_PER_CLK |
1 |
C_NUM_IDELAYCTRL |
1 |
C_NUM_PORTS |
2 |
C_PACKAGE |
ff1136 |
C_PI0_ADDRACK_PIPELINE |
1 |
C_PI0_PM_DC_CNTR |
1 |
C_PI0_PM_USED |
1 |
C_PI0_RD_FIFO_APP_PIPELINE |
1 |
C_PI0_RD_FIFO_MEM_PIPELINE |
1 |
C_PI0_RD_FIFO_TYPE |
BRAM |