MODIFICATION HISTORY:
Ver Who Date Changes ----- ---- -------- ----------------------------------------------- 1.00a mta 02/24/07 First release 2.00a mta 10/24/07 Added support for Performance Monitoring and Static Phy 3.00a sdm 12/16/08 Added support for debug registers
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Calibration Reset Control Reg |
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Register default on reset mask |
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Debug Registers CTRL interface status |
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Device family |
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ECC CTRL interface status |
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Memory type (SDRAM/DDR/ DDR2) |
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External memory interface width |
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MPMC CTRL interface status |
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Number of ports |
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Static PHY CTRL interface status |
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PM CTRL interface status |
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MPMC Control/Status Reg |
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Global Intr Enable |
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Device Global Interrupt Enable Reg |
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debug access to the ECC byte lane |
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ECC Debug Register |
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Data read from ECC byte lane on the first byte of the data in the 4 beat memory burst |
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Data read from ECC byte lane on the second byte of the data in the 4 beat memory burst |
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Data read from ECC byte lane on the third byte of the data in the 4 beat memory burst |
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Data read from ECC byte lane on the fourth byte of the data in the 4 beat memory burst |
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ECC Read Data Register |
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ECC Write Data Register |
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ECC Error Address Register |
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Force double bit error |
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Force parity error |
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Force single bit error |
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ECC Control Register |
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ECC read enable |
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ECC write enable |
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ECC Double Error Count Register |
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ECC Parity Field Error Count Reg |
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ECC Single Error Count Register |
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Double bit error |
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Error Transaction Rd/Wr |
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Error Transc Rd/Wr shift |
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Error Transaction Size |
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Error Transaction shift |
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ECC Status Register |
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Parity field bit error |
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Single bit error |
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Single bit error syndrome |
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Single error synd shift |
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IP Interrupt Enable Register |
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IP Interrupt Status Register |
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Double bit error interrupt |
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Parity field error interrupt |
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Single bit error interrupt |
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Read a value from a MPMC register. A 32 bit read is performed.
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Write a value to a MPMC register. A 32 bit write is performed.
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Read Access |
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Address Offset between data bins of different Access types |
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Write Access |
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Highest Bin Number |
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Lowest Bin Number |
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Address Offset between data bins of different Ports |
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Qualifier 0 - Byte to Double words |
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Qualifier 1 - Cache Line 4 |
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Qualifier 2 - Cache Line 8 |
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Qualifier 3 - Burst 16 |
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Qualifier 4 - Burst 32 |
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Qualifier 5 - Burst 64 |
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Address Offset between data bins of different Qualifiers |
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PM Clear Register |
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PM Control Register |
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PM Port-0 Data Bin-0 Register |
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PM Dead Cycle Counter Port 0 |
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PM Global Cycle Counter Register |
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PM0 Mask |
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PM1 Mask |
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PM2 Mask |
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PM3 Mask |
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PM4 Mask |
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PM5 Mask |
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PM6 Mask |
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PM7 Mask |
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PM All Mask |
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PM Status Register |
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S3 Calibration Register |
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S3 Calibration Status Register |
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Enable signal for strobe tap selection |
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Enable signal for rst_dqs_div tap selection |
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Tap values for rst_dqs_div |
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Tap values for strobes |
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Counter used in the calibration logic |
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Tap value to delay the strobe and rst_dqs_div |
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Enable signal for dbg_trans_two detect |
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Number of LUTs in the clock phase |
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To stop new tap_values from calibration logic to strobe and rst_dqs_div during memory read operations |
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Asserted when the first transition is detected |
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Asserted when the second transition is detected |
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DCM Phase shift Done |
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DCM Phase shift |
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DCM Phase shift Increment/Decrement |
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DCM Tap Value Mask |
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First Reset of Phy |
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Init Done |
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Static Phy Control Register |
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Read Data Clk Edge |
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Read Data Clk Shift |
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Read Enable Delay |
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Read Enable Delay |
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V4 Calibration DQ TAP Count0 Register |
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V4 Calibration DQS Group0 Register |
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V4 Calibration DQS TAP Count0 Register |
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V4 Calibration Register |
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V4 Calib Status Register |
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V4 Calibration bit alignment of 8 bits within the byte |
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Relative alignment of bytes for DQS group in V4 |
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Final read capture MUX set for positive or negative edge capture for DQS group in V4 |
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Number of cycles after read command until read data is valid for DQS group in V4 |
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IDELAY tap count dec |
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IDELAY tap count inc |
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IDELAY tap count |
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Delay enable |
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IDELAY tap count dec |
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IDELAY tap count inc |
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IDELAY tap count |
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V4 MPMC INIT DONE signal |
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V$ MPMC INIT DONE val when FORCE_INITDONE = 1 |
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V4 Hardware calibration on MPMC reset |
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V4 Status of MPMC_Idelayctrl_Rdy_I |
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V4 Status of MPMC_Idelayctrl_Rdy_O |
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V4 MIG h/w calibration initialization status |
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V4 tap control and pattern compare calibration completion status (1 bit per dqs bit) |
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V4 Pattern compare error completion status (1 bit per dqs bit) |
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V4 Calibration process of center-aligning DQS with respect to clock |
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Calibration DQ TAP Count0 Register |
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V5 Calibration DQS Group0 Register |
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V5 Calibration DQS TAP Count0 Register |
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V5 Calibration GATE TAP Count0 Register |
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V5 Calibration Register |
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V5 Calib Status Register |
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Number of cycles after read command until clock enable for DQ byte group is de-asserted to prevent post amble glitch for DQS group in V5 |
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Final read capture MUX set for positive or negative edge capture for DQS group in V5 |
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Number of cycles after read command until read data is valid for DQS group in V5 |
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IDELAY tap count dec |
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IDELAY tap count inc |
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IDELAY tap count |
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IDELAY tap count dec |
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IDELAY tap count inc |
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IDELAY tap count |
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IDELAY tap count dec |
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IDELAY tap count inc |
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IDELAY tap count |
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V5 MPMC INIT DONE signal |
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V5 MPMC INIT DONE val when FORCE_INITDONE = 1 |
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V5 Hardware calibration on MPMC reset |
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V5 Status of MPMC_Idelayctrl_Rdy_I |
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V5 Status of MPMC_Idelayctrl_Rdy_O |
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V5 MIG h/w calibration initialization status |
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Calibration error index |
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V5 Calibration complete status |
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V5 4-bit calibration error status |
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