MODIFICATION HISTORY:
Ver Who Date Changes ----- ---- -------- ----------------------------------------------- 1.00b jhl 04/24/02 First release 1.10b mta 03/21/07 Updated to new coding style
Register Offset Definitions | |
Register offsets within a timer counter, there are multiple timer counters within a single device | |
#define | XTC_TCSR_OFFSET |
#define | XTC_TLR_OFFSET |
#define | XTC_TCR_OFFSET |
Control Status Register Bit Definitions | |
Control Status Register bit masks Used to configure the timer counter device. | |
#define | XTC_CSR_ENABLE_ALL_MASK |
#define | XTC_CSR_ENABLE_PWM_MASK |
#define | XTC_CSR_INT_OCCURED_MASK |
#define | XTC_CSR_ENABLE_TMR_MASK |
#define | XTC_CSR_ENABLE_INT_MASK |
#define | XTC_CSR_LOAD_MASK |
#define | XTC_CSR_AUTO_RELOAD_MASK |
#define | XTC_CSR_EXT_CAPTURE_MASK |
#define | XTC_CSR_EXT_GENERATE_MASK |
#define | XTC_CSR_DOWN_COUNT_MASK |
#define | XTC_CSR_CAPTURE_MODE_MASK |
Defines | |
#define | XTC_DEVICE_TIMER_COUNT |
#define | XTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) |
#define | XTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite) |
#define | XTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue) |
#define | XTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mGetTimerCounterReg(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mSetLoadReg(BaseAddress, TmrCtrNumber, RegisterValue) |
#define | XTmrCtr_mGetLoadReg(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mEnable(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mDisable(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mEnableIntr(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mDisableIntr(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mLoadTimerCounterReg(BaseAddress, TmrCtrNumber) |
#define | XTmrCtr_mHasEventOccurred(BaseAddress, TmrCtrNumber) |
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In compare mode, configures the timer counter to reload from the Load Register. The default mode causes the timer counter to hold when the compare value is hit. In capture mode, configures the timer counter to not hold the previous capture value if a new event occurs. The default mode cause the timer counter to hold the capture value until recognized. |
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Enables the timer to capture the timer counter value when the external capture line is asserted. The default mode is compare mode. |
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Configures the timer counter to count down from start value, the default is to count up. |
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Enables all timer counters |
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Enables the interrupt output. |
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Enables the Pulse Width Modulation |
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Enables only the specific timer |
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Enables the external input to the timer counter. |
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Enables the external generate output for the timer. |
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If bit is set, an interrupt has occured. If set and '1' is written to this bit position, bit is cleared. |
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Loads the timer using the load value provided earlier in the Load Register, XTC_TLR_OFFSET. |
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Defines the number of timer counters within a single hardware device. This number is not currently parameterized in the hardware but may be in the future. |
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Timer counter register |
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Control/Status register |
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Load register |
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Read one of the timer counter registers.
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Disable a timer counter such that it stops running.
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Disable the interrupt for a timer counter.
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Enable a timer counter such that it starts running.
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Enable the interrupt for a timer counter.
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Get the Control Status Register of a timer counter.
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Get the Load Register of a timer counter.
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Get the Timer Counter Register of a timer counter.
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Determine if a timer counter event has occurred. Events are defined to be when a capture has occurred or the counter has roller over.
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Cause the timer counter to load it's Timer Counter Register with the value in the Load Register.
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Set the Control Status Register of a timer counter to the specified value.
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Set the Load Register of a timer counter to the specified value.
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Write a specified value to a register of a timer counter.
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