### Xilinx Processor IP Library

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# mpmc v3_01_a

The Xilinx XMpmc driver supports the following functionality in the Xilinx Multi-Port Memory Controller (MPMC), a soft IP core designed for Xilinx FPGAs:

- Error Correction Code (ECC) capability
- Performance Monitoring
- Static PHY

The device driver is not necessary for the MPMC device unless one of the three functionalities is enabled in the MPMC device.

This header file contains the interfaces for the MPMC device driver.

ECC is a mode that detects and corrects single memory errors and detects the double memory errors. The XMpmc device driver provides the following abilities for ECC:

- Enable and Disable ECC mode in Read logic/Write logic or both.
- Enable and Disable interrupts for specific ECC errors.
- Error injection for testing of ECC mode.
- Statistics for specific ECC errors detected.
- Information about address where the last error was detected.

The XMpmc device driver provides the following abilities for Performance Monitoring:

- Enable and Disable Performance Monitoring.
- Clear the Performance Monitoring Data Bins.
- Get and Clear the the Performance Monitoring Data Bins Clear Status.
- Get the Global Cycle Count, Dead Cycle Count and Peformance Monitoring Data for the Data Bins.

The XMpmc device driver provides the following abilities for Static Phy:

- Read and Write to the Static PHY register.

The XMpmc device driver provides the following abilities for Debug Registers:

- Read and Write to the Calibration Reset Control register.
- Read and Write to the Calibration register.
- Read the Calibration Status register.
- Read and Write to the ECC Debug register.
- Read the ECC Read Data register.
- Read and Write to the ECC Write Data register.
- Read and Write to the Calibration DQS Group register.
- Read and Write to the Calibration DQS TAP Count register.
- Read and Write to the Calibration Gate TAP Count register.
- Read and Write to the Calibration DQ TAP Count register.

The following Debug registers are available when the Processor is Virtex4/Virtex5.

- Calibration DQS Group register.
- Calibration DQ TAP Count register.

The following Debug registers are available only when the Processor is Virtex5.

- Calibration DQS TAP Count register.
- Calibration Gate TAP Count register.

Initialization and Configuration

The device driver enables higher layer software (for example, an application) to communicate with the MPMC device.

XMpmc_CfgInitialize() API is used to initialize the XMpmc device instance. The user needs to first call the XMpmc_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XMpmc_CfgInitialize() API.

Interrupts

The MPMC device has one physical interrupt which must be connected to the interrupt controller in the system. The driver does not provide any interrupt handler for handling the interrupt. The users of this driver must connect their own interrupt handler with the interrupt system.

Asserts

Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.

Threads

This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.

Hardware Parameters Needed

To use this driver with the MPMC device one of the following functionalities must be enabled:

- ECC capability
- Performance Monitoring
- Static PHY

The interrupt capability for the device must be enabled in the hardware if interrupts are to be used with the driver. The interrupt functions of the device driver will assert when called if interrupt support is not present in the hardware.

The ability to force errors is a test mode and it must be enabled in the hardware if the control register is to be used to force ECC errors.

     MODIFICATION HISTORY:

     Ver   Who  Date     Changes
     ----- ---- -------- -----------------------------------------------
     1.00a mta  02/24/07 First release
     2.00a mta  10/24/07 Added support for Performance Monitoring and Static PHY
     3.00a sdm  12/16/08 Added support for Debug Registers
     3.01a sdm  07/14/09 Updated the driver Tcl to use the new parameters
                         C_MPMC_SW_BASEADDR and C_MPMC_SW_HIGHADDR when
                         C_ALL_PIMS_SHARE_ADDRESSES=0

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