### Xilinx Processor IP Library

Software Drivers

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# xgpio_l.h File Reference

## Detailed Description

This header file contains identifiers and driver functions (or macros) that can be used to access the device. The user should refer to the hardware device specification for more details of the device operation.

The macros that are available in this file use a multiply to calculate the addresses of registers. The user can control whether that multiply is done at run time or at compile time. A constant passed as the channel parameter will cause the multiply to be done at compile time. A variable passed as the channel parameter will cause it to occur at run time.

     MODIFICATION HISTORY:

     Ver   Who  Date     Changes
     ----- ---- -------- -----------------------------------------------
     1.00a jhl  04/24/02 First release of low level driver
     2.00a jhl  11/26/03 Added support for dual channels and interrupts. This
                         change required the functions to be changed such that
                         the interface is not compatible with previous versions.
                         See the examples in the example directory for macros
                         to help compile an application that was designed for
                         previous versions of the driver. The interrupt registers
                         are accessible using the ReadReg and WriteReg macros and
                         a channel parameter was added to the other macros.
     2.11a mta  03/21/07 Updated to new coding style
     2.12a sv   11/21/07 Updated driver to support access through DCR bus

## Registers
Register offsets for this device.
#define | XGPIO_DATA_OFFSET
#define | XGPIO_TRI_OFFSET
#define | XGPIO_DATA2_OFFSET
#define | XGPIO_TRI2_OFFSET
#define | XGPIO_GIE_OFFSET
#define | XGPIO_ISR_OFFSET
#define | XGPIO_IER_OFFSET
## Interrupt Status and Enable Register bitmaps and masks
Bit definitions for the interrupt status register and interrupt enable registers.
#define | XGPIO_IR_MASK
#define | XGPIO_IR_CH1_MASK
#define | XGPIO_IR_CH2_MASK
## Global Interrupt Enable Register bitmaps and masks
Bit definitions for the Global Interrupt Enable register
#define | XGPIO_GIE_GINTR_ENABLE_MASK
## Defines
#define | XGpio_mWriteReg(BaseAddress, RegOffset, Data)
#define | XGpio_mReadReg(BaseAddress, RegOffset)
#define | XGpio_mGetDataReg(BaseAddress, Channel)
#define | XGpio_mSetDataReg(BaseAddress, Channel, Data)

## Define Documentation

#define XGPIO_DATA2_OFFSET

| Data register for 2nd channel

#define XGPIO_DATA_OFFSET

| Data register for 1st channel

#define XGPIO_GIE_OFFSET

| Glogal interrupt enable register

#define XGPIO_IER_OFFSET

| Interrupt enable register

#define XGPIO_IR_CH1_MASK

| Mask for the 1st channel

#define XGPIO_IR_CH2_MASK

| Mask for the 2nd channel

#define XGPIO_IR_MASK

| Mask of all bits

#define XGPIO_ISR_OFFSET

| Interrupt status register

#define XGpio_mGetDataReg | ( | BaseAddress,
|  | Channel |  | ) |

  | Get the data register of the specified GPIO channel. Parameters:
  | BaseAddress | contains the base address of the GPIO device.
  | Channel | contains the channel (1 or 2) to operate on.
Returns: The contents of the data register. Note: C-style signature: u32 XGpio_mGetDataReg(u32 BaseAddress, unsigned Channel)

#define XGpio_mReadReg | ( | BaseAddress,
|  | RegOffset |  | ) |

  | Read a value from a GPIO register. A 32 bit read is performed. If the GPIO component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0. Parameters:
  | BaseAddress | is the base address of the GPIO device.
  | Register | is the register offset from the base to read from.
Returns: Data read from the register. Note: C-style signature: u32 XGpio_mReadReg(u32 BaseAddress, u32 RegOffset)

#define XGpio_mSetDataReg | ( | BaseAddress,
|  | Channel,
|  | Data |  | ) |

  | Set the data register of the specified GPIO channel. Parameters:
  | BaseAddress | contains the base address of the GPIO device.
  | Channel | contains the channel (1 or 2) to operate on.
  | Data | is the value to be written to the data register.
Returns: None. Note: C-style signature: void XGpio_mSetDataReg(u32 BaseAddress, unsigned Channel, u32 Data)

#define XGpio_mWriteReg | ( | BaseAddress,
|  | RegOffset,
|  | Data |  | ) |

  | Write a value to a GPIO register. A 32 bit write is performed. If the GPIO component is implemented in a smaller width, only the least significant data is written. Parameters:
  | BaseAddress | is the base address of the GPIO device.
  | RegOffset | is the register offset from the base to write to.
  | Data | is the data written to the register.
Returns: None. Note: C-style signature: void XGpio_mWriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

#define XGPIO_TRI2_OFFSET

| I/O direction reg for 2nd channel

#define XGPIO_TRI_OFFSET

| I/O direction reg for 1st channel

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